Abstract： A novel universal approach for design and implementation of chaotic digital communication system based on IEEE-754 standard and field programmable gate array technology (FPGA) is proposed, combing chaos encryption with traditional cipher realization. By using the Euler algorithm and appropriate discrete processing, the continuous chaotic system is converted to a discrete chaotic system. Using FPGA hardware design system, digital chaotic sequence is generated as the key. Scrambling and expansion encryption algorithm is realized and analyzed. Driven and response of secure communication system is designed by constructing a loop including the signal and achieving chaotic synchronization between sender and receiver. Taking grid Chua chaotic system as an example, the secure communication system using FPGA hardware platform is implemented. The technical development process, algorithm flow chart, hardware design and realization result are also given.
grid multi-scroll Chua’s circuitscrambling and expanding matrixfield programmable gate array technologychaotic digital communication system