一种考虑硅通孔电阻-电容效应的三维互连线模型

doi:10.7498/aps.61.068001

摘要
参考文献(20)
相关文章 (12)

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摘要：

硅通孔(TSV)是三维集成电路的一种主流技术.基于TSV寄生参数提取模型,对不同物理尺寸的TSV电阻-电容(RC)参数进行提取,采用Q3D仿真结果验证了模型精度.分析TSVRC效应对片上系统的性能及功耗影响,推导了插入缓冲器的三维互连线延时与功耗的解析模型.在45nm互补金属氧化物半导体工艺下,对不同规模的互连电路进行了比较分析.模拟结果显示,TSVRC效应导致互连延时平均增加10%,互连功耗密度平均提高21%;电路规模越小,TSV影响愈加显著.在三维片上系统前端设计中,包含TSV寄生参数的互连模型将有助于设计者更加精确地预测片上互连性能.

关键词：三维集成硅通孔互连延时功耗

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	钱利波
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	杨银堂

Abstract：

Through-silicon-via (TSV) is one of the major design techniques in three- dimensional integrated circuit (3D IC). Based on the parasitic parameter extraction model, the parasitic resistance-capacitance (RC) parameters for different size TSVs are acquired and validated with Q3D simulation data. Using the results of this model, closed-form delay and power consumption expressions for buffered interconnect used in 3D IC are presented. Comparative results with 3D net without TSV in various cases show that TSV RC effect has a huge influence on delay and power of 3D IC, which leads maximum delay and power comsumption to extra increase 10% and 21\% on average, respectively. It is crucial to correctly establish a TSV-aware 3D interconnect model in 3D IC front-end design.

Keywords： 3D integrated circuit TSV interconnect delay power consumption

收稿日期: 2011-05-26

PACS:	80.30.-r
	84.40.Bw

基金:

国家自然科学基金(批准号: 60725415, 60676009)和国家科技重大专项(批准号: 2009ZX01034-002-001-005)资助的课题.

通讯作者: 朱樟明,zmyh@263.net E-mail: zmyh@263.net

引用本文:

钱利波,朱樟明,杨银堂. 一种考虑硅通孔电阻-电容效应的三维互连线模型. 物理学报, 2012, 61(6): 068001.

Cite this article:

Qian Li-Bo,Zhu Zhang-Ming,Yang Yin-Tang. Through-silicon-via-aware interconnect prediction model for 3D integrated circuirt. Acta Phys. Sin., 2012, 61(6): 068001.

URL:

http://wulixb.iphy.ac.cn/CN/Y2012/V61/I6/068001 或 http://wulixb.iphy.ac.cn/CN/10.7498/aps.61.068001

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