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SOI部分耗尽SiGe HBT集电结空间电荷区模型

徐小波 张鹤鸣 胡辉勇 许立军 马建立

SOI部分耗尽SiGe HBT集电结空间电荷区模型

徐小波, 张鹤鸣, 胡辉勇, 许立军, 马建立
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  • SOI上的薄膜异质SiGe晶体管通过采用"折叠"集电极,已成功实现SOI上CMOS与HBT的兼容.本文结合SOI薄膜上的纵向SiGe HBT结构模型,提出了包含纵向、横向欧姆电阻和耗尽电容的"部分耗尽 (partially depleted) 晶体管"集电区简化电路模型.基于器件物理及实际考虑,系统建立了外延集电层电场、电势、耗尽宽度模型,并根据该模型对不同器件结构参数进行分析.结果表明,空间电荷区表现为本征集电结耗尽与MOS电容耗尽,空间电荷区宽度随集电结掺杂浓度减小而增大,随集电结反偏电压提高而增大,
    • 基金项目: 国家部委资助项目(批准号:51308040203, 6139801),中央高校基本科研业务费(批准号:72105499, 72104089)和陕西省自然科学基础研究计划(批准号:2010JQ8008)资助的课题.
    [1]

    Floyd B, Pfeiffer U, Reynolds S, Valdes-Garcia A, Haymes C, Katayama Y, Nakano D, Beukema T, Gaucher B, Soyuer M 2007 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems SiRF07 Long Beach, CA, United states, 2007 p213

    [2]

    Fleetwood D M, Thome F V, Tsao S S, Dressendorfer P V, Dandini V J, Schwank J R 1988 IEEE Trans. Nucl. Sci. 35 1099

    [3]

    Shahidi G G 2002 IBM Journal of Research and Development 46 121

    [4]

    Shahidi G G, Ajmera A, Assaderaghi F, Bolam R J, Leobandung E, Rausch W, Sankus D, Schepis D, Wagner L F, Kun W, Davari B 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, Piscataway, NJ, USA, Feb.15—17, 1999,p426

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    Larson L E 2000 International Electron Devices Meeting, Technical Digest. IEDM, San Francisco, CA, USA, Dec. 10—13, 2000 p737

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    Washio K, Ohue E, Shimamoto H, Oda K, Hayami R, Kiyota Y, Tanabe M, Kondo M, Hashimoto T, Harada, T 2002 IEEE Trans ED 49 271

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    Sato F, Hashimoto T, Tezuka H, Soda M, Suzaki T, Tatsumi T, Tashiro T 1999 IEEE Trans ED 46 1332

    [8]

    Cai J, Ajmera A, Ouyang Q Q, Oldiges P, Steigerwalt M, Stein K, Jenkins K, Shahidi G, Ning T H 2002 Symposium on VLSI Technology Digest of Technical Papers Honolulu, HI, United states, June 11—13, 2002 p172

    [9]

    Avenier G, Schwartzmann T, Chevalier P, Vandelle B, Rubaldo L, Dutartre D, Boissonnet L, Saguin F, Pantel R, Fregonese S, Maneux C, Zimmer T, Chantre A 2005 IEEE Bipolar/BiCMOS Circuits and Technol. Meeting Santa Barbara, CA, USA, October 9—11, 2005, p128.

    [10]

    Rücker H, Heinemann B, Barth R, Bolze D, Drews J, Fursenko O, Grabolla T, Haak U, Hppner W, Knoll D, Marschmeyer S, Mohapatra N, Richter H H, Schley P, Schmidt D, Tillack B, Weidner G, Wolansky D, Wulf H E, Yamamoto Y 2004 Technical Digest - International Electron Devices Meeting IEDM San Francisco CA, United states, Dec.13—15, 2004 p239

    [11]

    Ouyang Q Q, Cai J, Ning T, Oldiges P, Jeffery B J 2003 Proc. IEEE Bipolar/BiCMOS Circuits and Technol. Meeting BCTM Minneapolis, United states, Sep.29—Oct. 1,2002 p28

    [12]

    Cai J, Mahender K, Steigerwalt M, Ho H, Schonenberg K, Stein K, Chen H J, Jenkins K, Ouyang Q Q, Oldiges P, Ning T H 2003 Proc. IEEE Bipolar/BiCMOS Circuits and Technology Meeting BCTM Toulouse, France, 2003 p215

    [13]

    Cai J, Ning T H 2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings ICSICT Beijing, China, Oct. 18—21, 2004 p2102

    [14]

    Avenier G, Chevalier P, Vandelle B, Lenoble D, Saguin F, Frégonèse S, Zimmer T, Chantre A 2005 Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference Grenoble, France, Sep. 12—16, 2005 p133

    [15]

    Avenier G, Frégonè S, Chevalier P, Bustos J, Saguin F, Schwartzmann T, Maneux C, Zimmer T, Chantre A 2008 IEEE Transactions on Electron Devices 55 585

    [16]

    Avenier G, Diop M, Chevalier P, Troillard G, Loubet N, Bouvier J, Depoyan Linda, Derrier N, Buczko M, Leyris C, Boret S, Montusclat S, Margain A, Pruvost S, Nicolson S T, Yau K H K, Revil N, Gloria D, Dutartre D, Voinigescu S P, Chantre, A 2009 IEEE Journal of Solid-State Circuits 44 2312

    [17]

    Chen T B, Bellini M, Zhao E H, Comeau J P, Sutton A K, Grens C M, Cressler J D, Cai J, Ning T H 2005 Proc. IEEE Bipolar/BiCMOS Circuits and Technology Meeting BCTM Santa Barbara, CA, USA, Oct. 9—11, 2005 p256

    [18]

    Bellini M, Cressler J D, Cai J 2007 Proc. IEEE Bipolar/ BiCMOS Circuits and Technology Meeting BCTM Boston MA, USA, Sep. 30—Oct.2, 2007 p234

    [19]

    Bellini M, Chen T B, Zhu C D, Cressler J D, Cai J 2006 IEEE Bipolar/BiCMOS Circuits and Technology Meeting BCTM Maastricht Netherlands Oct. 8—10 2006 p4

    [20]

    Chen T B, Sutton A K, Bellini M, Haugerud B M, Comeau J P, Liang Q Q, Cressler J D, Cai J, Ning T H, Marshall P W, Marshall C J 2005 IEEE Transactions on Nuclear Science 52 2353

    [21]

    Vanhoucke T, Boots H M J, Van Noort W D 2004 IEEE Electron Device Letters 25 150

    [22]

    Hu H Y, Zhang H M, Lü Y, Dai X Y, Hou H, Ou J F, Wang W, Wang X Y 2006 Acta Phys. Sin. 55 403 (in Chinese)[胡辉勇、张鹤鸣、吕 懿、戴显英、侯 慧、区健锋、王 伟、王喜媛 2006 物理学报 55 403]

    [23]

    Lü Y, Zhang H M, Dai X Y, Hu H Y, Shu B 2004 Acta Phys. Sin. 53 3239 (in Chinese)[吕 懿、张鹤鸣、戴显英、胡辉勇、舒 斌 2004 物理学报 53 3239]

    [24]

    Toorn R V, Paasschenss J C J, Kloosterman W J 2008 The Mextram Bipolar Transistor Model level 504.7, Mextram definition document , 2008 Delft University of Technology

    [25]

    Frégonè S, Avenier G, Maneux C, Chantre A 2006 IEEE Trans ED 53 296

    [26]

    Kirk C T 1962 IRE Trans. Electron Devices 9 164

    [27]

    Shi M, Wu G Y 2008 Semiconductor Device Physics (Xi'an: Xi'an Jiaotong University Press)p256—264(in Chinese)[施敏著 伍国珏译 2008 半导体器件物理(西安:西安交通大学出版社)第256—264页]

  • [1]

    Floyd B, Pfeiffer U, Reynolds S, Valdes-Garcia A, Haymes C, Katayama Y, Nakano D, Beukema T, Gaucher B, Soyuer M 2007 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems SiRF07 Long Beach, CA, United states, 2007 p213

    [2]

    Fleetwood D M, Thome F V, Tsao S S, Dressendorfer P V, Dandini V J, Schwank J R 1988 IEEE Trans. Nucl. Sci. 35 1099

    [3]

    Shahidi G G 2002 IBM Journal of Research and Development 46 121

    [4]

    Shahidi G G, Ajmera A, Assaderaghi F, Bolam R J, Leobandung E, Rausch W, Sankus D, Schepis D, Wagner L F, Kun W, Davari B 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, Piscataway, NJ, USA, Feb.15—17, 1999,p426

    [5]

    Larson L E 2000 International Electron Devices Meeting, Technical Digest. IEDM, San Francisco, CA, USA, Dec. 10—13, 2000 p737

    [6]

    Washio K, Ohue E, Shimamoto H, Oda K, Hayami R, Kiyota Y, Tanabe M, Kondo M, Hashimoto T, Harada, T 2002 IEEE Trans ED 49 271

    [7]

    Sato F, Hashimoto T, Tezuka H, Soda M, Suzaki T, Tatsumi T, Tashiro T 1999 IEEE Trans ED 46 1332

    [8]

    Cai J, Ajmera A, Ouyang Q Q, Oldiges P, Steigerwalt M, Stein K, Jenkins K, Shahidi G, Ning T H 2002 Symposium on VLSI Technology Digest of Technical Papers Honolulu, HI, United states, June 11—13, 2002 p172

    [9]

    Avenier G, Schwartzmann T, Chevalier P, Vandelle B, Rubaldo L, Dutartre D, Boissonnet L, Saguin F, Pantel R, Fregonese S, Maneux C, Zimmer T, Chantre A 2005 IEEE Bipolar/BiCMOS Circuits and Technol. Meeting Santa Barbara, CA, USA, October 9—11, 2005, p128.

    [10]

    Rücker H, Heinemann B, Barth R, Bolze D, Drews J, Fursenko O, Grabolla T, Haak U, Hppner W, Knoll D, Marschmeyer S, Mohapatra N, Richter H H, Schley P, Schmidt D, Tillack B, Weidner G, Wolansky D, Wulf H E, Yamamoto Y 2004 Technical Digest - International Electron Devices Meeting IEDM San Francisco CA, United states, Dec.13—15, 2004 p239

    [11]

    Ouyang Q Q, Cai J, Ning T, Oldiges P, Jeffery B J 2003 Proc. IEEE Bipolar/BiCMOS Circuits and Technol. Meeting BCTM Minneapolis, United states, Sep.29—Oct. 1,2002 p28

    [12]

    Cai J, Mahender K, Steigerwalt M, Ho H, Schonenberg K, Stein K, Chen H J, Jenkins K, Ouyang Q Q, Oldiges P, Ning T H 2003 Proc. IEEE Bipolar/BiCMOS Circuits and Technology Meeting BCTM Toulouse, France, 2003 p215

    [13]

    Cai J, Ning T H 2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings ICSICT Beijing, China, Oct. 18—21, 2004 p2102

    [14]

    Avenier G, Chevalier P, Vandelle B, Lenoble D, Saguin F, Frégonèse S, Zimmer T, Chantre A 2005 Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference Grenoble, France, Sep. 12—16, 2005 p133

    [15]

    Avenier G, Frégonè S, Chevalier P, Bustos J, Saguin F, Schwartzmann T, Maneux C, Zimmer T, Chantre A 2008 IEEE Transactions on Electron Devices 55 585

    [16]

    Avenier G, Diop M, Chevalier P, Troillard G, Loubet N, Bouvier J, Depoyan Linda, Derrier N, Buczko M, Leyris C, Boret S, Montusclat S, Margain A, Pruvost S, Nicolson S T, Yau K H K, Revil N, Gloria D, Dutartre D, Voinigescu S P, Chantre, A 2009 IEEE Journal of Solid-State Circuits 44 2312

    [17]

    Chen T B, Bellini M, Zhao E H, Comeau J P, Sutton A K, Grens C M, Cressler J D, Cai J, Ning T H 2005 Proc. IEEE Bipolar/BiCMOS Circuits and Technology Meeting BCTM Santa Barbara, CA, USA, Oct. 9—11, 2005 p256

    [18]

    Bellini M, Cressler J D, Cai J 2007 Proc. IEEE Bipolar/ BiCMOS Circuits and Technology Meeting BCTM Boston MA, USA, Sep. 30—Oct.2, 2007 p234

    [19]

    Bellini M, Chen T B, Zhu C D, Cressler J D, Cai J 2006 IEEE Bipolar/BiCMOS Circuits and Technology Meeting BCTM Maastricht Netherlands Oct. 8—10 2006 p4

    [20]

    Chen T B, Sutton A K, Bellini M, Haugerud B M, Comeau J P, Liang Q Q, Cressler J D, Cai J, Ning T H, Marshall P W, Marshall C J 2005 IEEE Transactions on Nuclear Science 52 2353

    [21]

    Vanhoucke T, Boots H M J, Van Noort W D 2004 IEEE Electron Device Letters 25 150

    [22]

    Hu H Y, Zhang H M, Lü Y, Dai X Y, Hou H, Ou J F, Wang W, Wang X Y 2006 Acta Phys. Sin. 55 403 (in Chinese)[胡辉勇、张鹤鸣、吕 懿、戴显英、侯 慧、区健锋、王 伟、王喜媛 2006 物理学报 55 403]

    [23]

    Lü Y, Zhang H M, Dai X Y, Hu H Y, Shu B 2004 Acta Phys. Sin. 53 3239 (in Chinese)[吕 懿、张鹤鸣、戴显英、胡辉勇、舒 斌 2004 物理学报 53 3239]

    [24]

    Toorn R V, Paasschenss J C J, Kloosterman W J 2008 The Mextram Bipolar Transistor Model level 504.7, Mextram definition document , 2008 Delft University of Technology

    [25]

    Frégonè S, Avenier G, Maneux C, Chantre A 2006 IEEE Trans ED 53 296

    [26]

    Kirk C T 1962 IRE Trans. Electron Devices 9 164

    [27]

    Shi M, Wu G Y 2008 Semiconductor Device Physics (Xi'an: Xi'an Jiaotong University Press)p256—264(in Chinese)[施敏著 伍国珏译 2008 半导体器件物理(西安:西安交通大学出版社)第256—264页]

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  • 收稿日期:  2010-06-21
  • 修回日期:  2010-10-13
  • 刊出日期:  2011-07-15

SOI部分耗尽SiGe HBT集电结空间电荷区模型

  • 1. 西安电子科技大学微电子学院,宽禁带半导体材料与器件重点实验室,西安 710071
    基金项目: 

    国家部委资助项目(批准号:51308040203, 6139801),中央高校基本科研业务费(批准号:72105499, 72104089)和陕西省自然科学基础研究计划(批准号:2010JQ8008)资助的课题.

摘要: SOI上的薄膜异质SiGe晶体管通过采用"折叠"集电极,已成功实现SOI上CMOS与HBT的兼容.本文结合SOI薄膜上的纵向SiGe HBT结构模型,提出了包含纵向、横向欧姆电阻和耗尽电容的"部分耗尽 (partially depleted) 晶体管"集电区简化电路模型.基于器件物理及实际考虑,系统建立了外延集电层电场、电势、耗尽宽度模型,并根据该模型对不同器件结构参数进行分析.结果表明,空间电荷区表现为本征集电结耗尽与MOS电容耗尽,空间电荷区宽度随集电结掺杂浓度减小而增大,随集电结反偏电压提高而增大,

English Abstract

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