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A analytic model for the threshold-voltage of novel high-speed semiconductor device IMOS

Li Yu-Chen Zhang He-Ming Zhang Yu-Ming Hu Hui-Yong Xu Xiao-Bo Qin Shan-Shan Wang Guan-Yu

A analytic model for the threshold-voltage of novel high-speed semiconductor device IMOS

Li Yu-Chen, Zhang He-Ming, Zhang Yu-Ming, Hu Hui-Yong, Xu Xiao-Bo, Qin Shan-Shan, Wang Guan-Yu
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  • A threshold voltage model is created by analyzing differents distributions of surface electric field and the condition of avalanche breakdown, based on the structure of a novel high speed semiconductor device p-IMOS in this paper. Model verification is carried out using the 2D device simulator ISE. By analyzing the model, the dependences of threshold voltage on drain-source voltage, Si layer thickness and gate length are studied. The results of the model are in good agreement with experimental results and ISE simulation results. The proposed model can also be easily used for the reasonable analysis and the design of p-IMOS.
    • Funds: Project supported by the National Ministries and Commissions (Grant Nos. 51308040203, 6139801), the Fundamental Research Funds for the Central Universities (Grant Nos. 72105499, 72104089), and the Natural Science Basic Research Plan in Shaanxi Province of China (Grant No.2010JQ8008).
    [1]

    Lundstrom M 2003 IEEE International Electron Devices Meeting Washington, DC, USA, 8—10 Dec. 2003, p789

    [2]

    Choi W Y, Choi B Y, Woo D S, Lee J D, Park B G 2003 IEEE Trans. Nanotechnol 2 210

    [3]

    Gopalakrishnan K, Griffin P B, Plummer J D 2002 IEEE International Electron Devices Meeting San Francisco, CA, USA 8—11 Dec. 2002 p289

    [4]

    Gopalakrishnan K, Griffin P B, Plummer J, Woo R, Jungemann C 2005 IEEE Trans. Electron Devices 52 77

    [5]

    Choi W Y, Choi B Y, Lee J D, Woo D S, Park B J 2004 Device Research Conference Notre Dame, IN, USA June 2004, p211

    [6]

    Choi W Y, Song J Y, Choi B Y, Lee J D, Park Y J, Park B J 2004 International Electron Devices Meeting San Francisco, CA, USA 13—15 Dec. 2004 p203

    [7]

    Choi W Y, Lee J D, Park B G 2006 Journal of Semiconductor Technology and Science 6 43

    [8]

    Gopalakrishnan K, Woo R, Jungemann C, Griffin P B, Plummer J 2005 IEEE Trans. Electron Devices 52 69

    [9]

    Hou C S, Wu C Y 1995 IEEE Trans. Electron Devices 42 2156

    [10]

    Li Y P, Xu J P, Chen W B, Zou X 2005 Microelectronics 35 0040 (in Chinese) [李艳萍, 徐静平, 陈卫兵, 邹 晓 2005 微电子学 35 0040]

    [11]

    Li Y P, Xu J P, Chen W B, Ji F 2006 Acta Phys.Sin. 55 3670 (in Chinese) [李艳萍, 徐静平, 陈卫兵, 许胜国, 季峰 2006 物理学报 55 3670]

    [12]

    Zhang H M, Cui X Y, Hu H Y, Dai X Y, Xuan R X 2007 Acta Phys.Sin. 56 3504 (in Chinese) [张鹤鸣, 崔晓英, 胡辉勇, 戴显英, 宣荣喜 2007 物理学报 56 3504]

    [13]

    Zhang Z F, Zhang H M, Hu H Y, Xuan R X, Song J J 2009 Acta Phys.Sin. 58 4948 (in Chinese) [张志锋, 张鹤鸣, 胡辉勇, 宣荣喜, 宋建军 2009 物理学报 58 4948]

    [14]

    Qin S S, Zhang H M, Hu H Y, Dai X Y, Xuan R X, Shu B 2010 Chin. Phys. B 19 117309

    [15]

    Qu J T, Zhang H M, Wang G Y, Wang X Y, Hu H Y 2011 Chin. Phys. 60 058502

    [16]

    Hassani F A, Fathipour M, Mehran M 2007 IEEE AFRICON Windhoek, South Africa September 26—28, 2007

    [17]

    Mayer F, Royer C L, Carval G L, Clavelier L, Deleonibus S 2006 IEEE Trans. Electron Devices 53 1852

  • [1]

    Lundstrom M 2003 IEEE International Electron Devices Meeting Washington, DC, USA, 8—10 Dec. 2003, p789

    [2]

    Choi W Y, Choi B Y, Woo D S, Lee J D, Park B G 2003 IEEE Trans. Nanotechnol 2 210

    [3]

    Gopalakrishnan K, Griffin P B, Plummer J D 2002 IEEE International Electron Devices Meeting San Francisco, CA, USA 8—11 Dec. 2002 p289

    [4]

    Gopalakrishnan K, Griffin P B, Plummer J, Woo R, Jungemann C 2005 IEEE Trans. Electron Devices 52 77

    [5]

    Choi W Y, Choi B Y, Lee J D, Woo D S, Park B J 2004 Device Research Conference Notre Dame, IN, USA June 2004, p211

    [6]

    Choi W Y, Song J Y, Choi B Y, Lee J D, Park Y J, Park B J 2004 International Electron Devices Meeting San Francisco, CA, USA 13—15 Dec. 2004 p203

    [7]

    Choi W Y, Lee J D, Park B G 2006 Journal of Semiconductor Technology and Science 6 43

    [8]

    Gopalakrishnan K, Woo R, Jungemann C, Griffin P B, Plummer J 2005 IEEE Trans. Electron Devices 52 69

    [9]

    Hou C S, Wu C Y 1995 IEEE Trans. Electron Devices 42 2156

    [10]

    Li Y P, Xu J P, Chen W B, Zou X 2005 Microelectronics 35 0040 (in Chinese) [李艳萍, 徐静平, 陈卫兵, 邹 晓 2005 微电子学 35 0040]

    [11]

    Li Y P, Xu J P, Chen W B, Ji F 2006 Acta Phys.Sin. 55 3670 (in Chinese) [李艳萍, 徐静平, 陈卫兵, 许胜国, 季峰 2006 物理学报 55 3670]

    [12]

    Zhang H M, Cui X Y, Hu H Y, Dai X Y, Xuan R X 2007 Acta Phys.Sin. 56 3504 (in Chinese) [张鹤鸣, 崔晓英, 胡辉勇, 戴显英, 宣荣喜 2007 物理学报 56 3504]

    [13]

    Zhang Z F, Zhang H M, Hu H Y, Xuan R X, Song J J 2009 Acta Phys.Sin. 58 4948 (in Chinese) [张志锋, 张鹤鸣, 胡辉勇, 宣荣喜, 宋建军 2009 物理学报 58 4948]

    [14]

    Qin S S, Zhang H M, Hu H Y, Dai X Y, Xuan R X, Shu B 2010 Chin. Phys. B 19 117309

    [15]

    Qu J T, Zhang H M, Wang G Y, Wang X Y, Hu H Y 2011 Chin. Phys. 60 058502

    [16]

    Hassani F A, Fathipour M, Mehran M 2007 IEEE AFRICON Windhoek, South Africa September 26—28, 2007

    [17]

    Mayer F, Royer C L, Carval G L, Clavelier L, Deleonibus S 2006 IEEE Trans. Electron Devices 53 1852

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    [7] Li Yan-Ping, Xu Jing-Ping, Chen Wei-Bing, Xu Sheng-Guo, Ji Feng. 2-D threshold voltage model for short-channel MOSFET with quantum-mechanical effects. Acta Physica Sinica, 2006, 55(7): 3670-3676. doi: 10.7498/aps.55.3670
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    [9] Li Li, Liu Hong-Xia, Yang Zhao-Nian. Threshold-voltage and hole-sheet-density model of quantum well Si/SiGe/Si p field effect transistor. Acta Physica Sinica, 2012, 61(16): 166101. doi: 10.7498/aps.61.166101
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  • Received Date:  22 April 2011
  • Accepted Date:  21 June 2011
  • Published Online:  15 April 2012

A analytic model for the threshold-voltage of novel high-speed semiconductor device IMOS

  • 1. Key Laboratory for Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi’an 710071, China
Fund Project:  Project supported by the National Ministries and Commissions (Grant Nos. 51308040203, 6139801), the Fundamental Research Funds for the Central Universities (Grant Nos. 72105499, 72104089), and the Natural Science Basic Research Plan in Shaanxi Province of China (Grant No.2010JQ8008).

Abstract: A threshold voltage model is created by analyzing differents distributions of surface electric field and the condition of avalanche breakdown, based on the structure of a novel high speed semiconductor device p-IMOS in this paper. Model verification is carried out using the 2D device simulator ISE. By analyzing the model, the dependences of threshold voltage on drain-source voltage, Si layer thickness and gate length are studied. The results of the model are in good agreement with experimental results and ISE simulation results. The proposed model can also be easily used for the reasonable analysis and the design of p-IMOS.

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