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The optimization of wire size has become a key technology for improving the chip system performance. Based on the influence of the wire size of interconnects on the delay, power, area and bandwidth, we propose an idea of optimal wire size based on multi-objective optimization method and obtain a multi-objective constrained analytical model by curve-fitting approach. The Hspice verification shows that the analytical model presented in this paper has a high precision and the average error is less than 5%. The algorithm is simple and can effectively compensate for deficiencies in application of quality factor approach and it can be applied to computer-aided design of nano-scale complementary metal-oxide semiconductor (CMOS) system chips.
[1] Shannon C 1948 Bell System Technology Journal 27 356
[2] Semiconductor Industry Assocaition 2007 International Technology Roadmap for Semiconductors
[3] Magdy A E 2003 13th ACM Great Lakes Symposium on VLSI Washington, DC, USA, April 28—29, 2003 p65
[4] Mui M L, Banerjee K, Mehrotra A 2004 IEEE Trans. Electron Devices 51 195
[5] Li X C 2005 IEEE Trans. Electron Devices 52 2272
[6] Banerjee K, Mehrotra A 2001 IEEE Symposium on VLSI Circuits Tokyo, Japan, June 14—16, 2001 p195
[7] Banerjee K, Mehrotra A 2002 IEEE Trans. Computer-Aided Design 21 904
[8] Banerjee K, Mehrotra A 2002 IEEE Trans. Electron Devices 49 2001
[9] Renatas J, Friedman E G 2009 The 19th ACM Great Lakes Symposium on VLSI Boston, USA, May 10—12 2009 p15
[10] Rajeev K D, Alyssa B A 2009 The 19th ACM Great Lakes Symposium on VLSI Boston, USA, May 10—12 2009 p275
[11] Avinash K K, Ashwini S 2009 The 14th Asia and South Pacific Design Automation Conference Yokohama, Japan, January 19—22, 2009 p1
[12] Zhang H B, Martin D F, Deng L 2009 The 2009 International Symposium on Physical Design San Diego, California, USA, March 29—April 1, 2009 p131
[13] Lee E, Lemieux G, Mirabbasi S 2008 Journal of Signal Processing Systems 56 57
[14] Carloni L, Andrew B K 2008 The 13th Asia and South Pacific Design Automation Conference Seoul, Korea, January 21—24, 2008 p258
[15] Ho Y J, Mak W K 2008 IEEE 2008 International Symposium on VLSI Design, Automation and Test Hsinchu, Taiwan, April 28—30, 2008 p287
[16] Chen G Q, Chen H 2007 The 2nd International Conference on Nano-Networks Catania, Italy, September 24—26, 2007 p22
[17] Zhu Z M, Qian L B, Yang Y T 2009 Chin. Phys. B 18 1188
[18] Zhu Z M, Qian L B, Yang Y T 2009 Acta Phys. Sin. 58 2631 (in Chinese) [朱樟明、钱利波、杨银堂 2009 物理学报 58 2631] 〖19] Li C, Liao H L and Huang R 2008 Chin. Phys. B 17 2730
[19] He L, Du L, Zhuang Y Q 2007 Acta Phys. Sin. 56 7176(in Chinese) [何 亮、杜 磊、庄奕琪 2007 物理学报 56 7176]
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[1] Shannon C 1948 Bell System Technology Journal 27 356
[2] Semiconductor Industry Assocaition 2007 International Technology Roadmap for Semiconductors
[3] Magdy A E 2003 13th ACM Great Lakes Symposium on VLSI Washington, DC, USA, April 28—29, 2003 p65
[4] Mui M L, Banerjee K, Mehrotra A 2004 IEEE Trans. Electron Devices 51 195
[5] Li X C 2005 IEEE Trans. Electron Devices 52 2272
[6] Banerjee K, Mehrotra A 2001 IEEE Symposium on VLSI Circuits Tokyo, Japan, June 14—16, 2001 p195
[7] Banerjee K, Mehrotra A 2002 IEEE Trans. Computer-Aided Design 21 904
[8] Banerjee K, Mehrotra A 2002 IEEE Trans. Electron Devices 49 2001
[9] Renatas J, Friedman E G 2009 The 19th ACM Great Lakes Symposium on VLSI Boston, USA, May 10—12 2009 p15
[10] Rajeev K D, Alyssa B A 2009 The 19th ACM Great Lakes Symposium on VLSI Boston, USA, May 10—12 2009 p275
[11] Avinash K K, Ashwini S 2009 The 14th Asia and South Pacific Design Automation Conference Yokohama, Japan, January 19—22, 2009 p1
[12] Zhang H B, Martin D F, Deng L 2009 The 2009 International Symposium on Physical Design San Diego, California, USA, March 29—April 1, 2009 p131
[13] Lee E, Lemieux G, Mirabbasi S 2008 Journal of Signal Processing Systems 56 57
[14] Carloni L, Andrew B K 2008 The 13th Asia and South Pacific Design Automation Conference Seoul, Korea, January 21—24, 2008 p258
[15] Ho Y J, Mak W K 2008 IEEE 2008 International Symposium on VLSI Design, Automation and Test Hsinchu, Taiwan, April 28—30, 2008 p287
[16] Chen G Q, Chen H 2007 The 2nd International Conference on Nano-Networks Catania, Italy, September 24—26, 2007 p22
[17] Zhu Z M, Qian L B, Yang Y T 2009 Chin. Phys. B 18 1188
[18] Zhu Z M, Qian L B, Yang Y T 2009 Acta Phys. Sin. 58 2631 (in Chinese) [朱樟明、钱利波、杨银堂 2009 物理学报 58 2631] 〖19] Li C, Liao H L and Huang R 2008 Chin. Phys. B 17 2730
[19] He L, Du L, Zhuang Y Q 2007 Acta Phys. Sin. 56 7176(in Chinese) [何 亮、杜 磊、庄奕琪 2007 物理学报 56 7176]
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