Considering the via effect and the heat fringing effect simultaneously，we proposed a compact interconnect temperature distribution model that can be applied for single interconnect and multilevel interconnects. Based on the 65 nm complementary metal-oxide semiconcluctor （CMOS） interconnect and material parameter，the temperature distribution of multilevel interconnects and single interconnect with different lengths was calculated. The results show that the temperature rise of global interconnect is still large when the via effect is considered，while the temperature rise of intermediate line and local line is quite small. For multilevel interconnects，the temperature rise in the uppermost layer interconnect is the largest. The temperature rise is approximately proportional to the thickness of insulator，and will rise higher if the thermal conductivity of dielectric materials becomes smaller. The proposed interconnect temperature distribution model can be used in nanometer CMOS computer-aided design.