Instability of a bottom gate microcrystalline silicon (μc-Si) thin film transistor (TFT), of which the active layer was deposited by very high frequency-plasma enhanced chemical vapor deposition with silane concentration of 4% diluted by H2, was measured and compared under two different gate bias stress conditions. A new instability phenomenon of TFT under the voltage bias stress of Vgs=Vds=10 V was found, where the ratio of the source-drain current of μc-Si TFT to its initial value decreases first, then stays flat for a period of time, then increases. However, under the voltage bias stress of Vgs=10 V(Vds＝0 V), the source-drain current of μc-Si TFT decreases as normal exponential decay. Analysis on the change of sub-threshold swing S and threshold voltage Vth with stress time indicated the recoverable degradation could have resulted from the electron trapping and releasing in μc-Si TFT treated by gate-bias stress with Vds≠0.