For modern processes at 90 nm and 65 nm technology nodes, the random yield loss can contribute much to the total yield loss. Hence, it is essential to calculate the critical area to analyse the areas of design, and make changes to improve the random yield. This study provides a novel weighted critical area （WCA） of arbitrary defect outline, which takes into account the clustering effect in the metal and empty regions of the chip as well as the size distribution of random defects. Then, two fast and accurate algorithms related-WCA extraction and its sort of WCAs are implemented, which can sever as a cost function of layout optimization for the random yield improvement.