With the integrated circuits processing stepping into nanometer scale, the interconnect Joule heat becomes significantly large. Based on the RLC π equivalent circuit, this paper proposes a novel accurate model to evaluate Joule heat power of interconnected line in VLSI. The shielding effect of the inductor and the non-ideal step stimulation are considered in the proposed model. The power consumption of a typical interconnected topology in 90 nm complementary metal-oxide semiconductor process is computed. The error between results of this proposed method and Hspice simulation is within 3% when the input signal’s delay time is within 1 ns. The proposed model can be used to estimate Joule heat consumption where rough heat control is needed, such as route structure in the network on chip.