A new test structure of gate controlled lateral PNP bipolar transistors designed and fabricated. An independent gate terminal is patterned on the oxide layer above the active base region of normal lateral PNP bipolar transistors. According to the gate sweep technique, by sweeping the voltage applied to the gate terminal, one can obtain the characteristic of base current versus gate voltage. The quantitative variations of oxide trapped charges and interface traps are analytically estimated and numerically calculated, and the radiation induced defects in the gate controlled lateral PNP bipolar transistors during 60Co-γ irradiation and annealing at room temperature are separated independently. The test structures and measurements of the bipolar transistors used in the experiment are introduced in detail in this paper.