Controllable growth of nanowires is a prerequisite for addressability and scalability of nanowire quantum devices. By combining top-down nanofabrication and bottom-up self-assembly, site-controlled GeSi nanowires with two (105) facets can be grown on Si (001) substrate with pre-patterned trenches. Trenches along the 100 or 010 crystallographic direction with 60 nm in width and 6 nm in height are fabricated on Si substrate by electron beam lithography and reactive ion etching. Subsequently, a 60-nm-thick Si buffer layer is grown at 330–400 ℃ on the patterned substrate to improve the surface quality. The facets at the tip of the trenches transform into (11n) after depositing the Si buffer layer. Self-organized GeSi nanowires form inside the trenches by depositing the 6-nm-thick Si₆₇Ge₃₃ film at 450 ℃ followed by 1 h annealing at 510 ℃. The GeSi nanowires are (105)-faceted with an average height of approximately 7 nm. Furthermore, we systematically study the influence of annealing temperature, Ge concentration and pattern period on the formation of site-controllable GeSi nanowire on a patterned Si (001) substrate. The GeSi nanowires can be formed only inside the trenches within a specific annealing temperature ranging from 500 ℃ to 520 ℃. It is also discovered that GeSi nanowires are very sensitive to Ge concentration, as they cannot form at lower Ge concentration due to a large nucleation energy barrier. In contrast, high Ge concentration will lead to the discontinuity of nanowires caused by higher atomic diffusion barrier. The generated GeSi nanowires in the trenches exhibit similar dimensions at different pattern periods, which indicates that the growth process is thermodynamically determined. Overall, we realize the controllable growth of the GeSi nanowires, while the length of nanowires can reach the millimeter even centimeter scales, replying on the patterned trench length. The above results offer a controllable growth method of the Ge nanowires, which could potentially lead to the scalability of the Ge quantum devices on Si substrates.