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中国物理学会期刊

基于工艺偏差的自旋转移矩辅助压控磁各向异性磁隧道结电学模型及其应用研究

CSTR: 32037.14.aps.71.20211700

Process deviation based electrical model of spin transfer torque assisted voltage controlled magnetic anisotropy magnetic tunnel junction and its application

CSTR: 32037.14.aps.71.20211700
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  • 自旋转移矩辅助电压调控磁各向异性磁隧道结(STT辅助VCMA-MTJ)作为非易失性全加器(NV-FA)中的核心部件, 具有切换速度快、功耗低, 稳定性好等优点, 将在物联网、人工智能等领域具有良好的发展前景. 然而随着磁隧道结(MTJ)尺寸的不断缩小以及芯片集成度的不断提高, 工艺偏差对MTJ及NV-FA电路性能的影响将变得越来越显著. 本文基于STT辅助VCMA-MTJ磁化动力学, 在充分考虑薄膜生长工艺偏差以及刻蚀工艺偏差影响的情况下, 建立了更为精确的STT辅助VCMA-MTJ电学模型, 研究了上述两种工艺偏差对MTJ及NV-FA电路性能的影响. 结果表明, 当自由层厚度偏差γtf ≥ 6%或氧化层厚度偏差γtox ≥ 0.7%时, MTJ将无法实现状态切换; 当隧穿磁阻率偏差β增大到30%时, 读取裕度SM将下降高达17.6%. 对于NV-FA电路, 通过增大电压Vb1以及写‘0’时增大电压Vb2或写‘1’时减小Vb2, 可有效降低非易失性加数写入错误率; 通过增大逻辑运算驱动电压Vdd, 可有效降低逻辑运算结果输出错误率.

     

    As one of the key components in the non-volatile full adder (NV-FA), spin transfer torque assisted voltage controlled magnetic anisotropy magnetic tunnel junction (STT assisted VCMA-MTJ) will possess superior development prospects in internet of things, artificial intelligence and other fields due to its fast switching speed, low power consumption and good stability. However, with the downscaling of magnetic tunnel junction (MTJ) and the improvement of chip integration, the effects of process deviation on the performances of MTJ device as well as NV-FA circuit become more and more important. Based on the magnetization dynamics of STT assisted VCMA-MTJ, a new electrical model of STT assisted VCMA-MTJ, in which the effects of the film growth variation and the etching variation are taken into account, is established to study the effects of the above deviations on the performances of MTJ device and NV-FA circuit. It is shown that the MTJ state fails to be switched under the free layer thickness deviation γtf ≥ 6% or the oxide layer thickness deviation γtox ≥ 0.7%. The sensing margin (SM) is reduced by 17.5% as the tunnel magnetoresistance ratio deviation β increases to 30%. The writing error rate can be effectively reduced by increasing Vb1, and increasing Vb2 when writing ‘0’ or reducing Vb2 when writing ‘1’ in the NV-FA circuit. The output error rate can also be effectively reduced by increasing the driving voltage of logical operation Vdd.

     

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