Three-dimensional (3D) NAND flash memory is a key technology in the field of mainstream memory solutions, which is primarily due to its extremely low bit cost. The architecture of 3D NAND, characterized by its vertically stacked design, substantially enhances the capacity of individual chips. This advancement is completely consistent with the demands for high-capacity data storage in contemporary environments, securing its widespread adoption in diverse application scenarios. As storage density increases, the complexity of process integration increases, bringing new challenges. The word lines in 3D NAND are typically filled by using gate replacement techniques, and compared with chemical vapor deposition (CVD), atomic layer deposition (ALD) is favored for its superior step-coverage, especially for depositing tungsten (W) at the gate. However, due to the complexity of the replacement gate deposition structure, fluorine (F) residues are found in the voids of the tungsten metal gate filling structure and diffuse into the surrounding structure under subsequent process conditions, corroding other films such as silicon oxide and degrading device performance and reliability. To alleviate the problem of fluorine attack, a thin layer of titanium nitride is usually deposited as a barrier layer before deposition of tungsten gate, which blocks the fluorine in the tungsten gate and prevents its diffusion into the oxide layer. Previously, there were studies to increase the ability to stop F diffusion by varying the thickness of the F blocking layer (TiN). However, increasing the thickness of TiN will further increase the complexity of high aspect ratio etching in the 3D NAND process, which will have adverse effect on subsequent processes. To further minimize the effect of fluorine erosion, residual fluorine elements can be removed by introducing annealing in the subsequent process flow. In the actual 3D NAND process, elemental fluorine (F) is adsorbed and accumulates on the TiN surface, and is further activated by subsequent high-temperature processes, leading to severe fluorine erosion. The delay between TiN deposition and subsequent processing steps is hypothesized to facilitate fluorine adsorption due to the oxidation of TiN. This work corroborates this hypothesis through first-principles calculations, and demonstrates the role of TiN oxidation in fluorine adsorption. In this work, we evaluate the effect of this oxidation on the fluorine-blocking effectiveness of the TiN barrier layer. We simulate the adsorption of fluorine-containing by-products on TiN and its oxides, providing theoretical insights into mitigating fluorine attack. The higher degree of oxidation of TiN is more likely to cause F adsorption, and Ti exposed surface TiN is more prone to oxidation, which is more likely to cause F adsorption in unoxidized condition and oxidized condition. Based on these insights, we implemente an ammonia purge treatment in 3D NAND manufacturing, which effectively minimizes fluorine attack, reducing the leakage probability of word line by 25% and wafer warpage by 43%.