The rising demand for high-performance computing has increased the need for low-voltage, high-current power management. In junction-isolated LDMOS devices, internal isolation structures inherently generate parasitic NPN and PNP bipolar junction transistors, which can degrade device switching performance and reliability. Under high-side (HS) conditions, conventional Gummel-Poon models often overestimate parasitic currents due to their inability to accurately capture the non-equilibrium carrier transport associated with effective base-width modulation and dual-injection effects, causing underestimation of conduction losses, overestimation of reverse recovery charge, and deviations in stress evaluation. To address this, a high-precision SPICE compact model incorporating a dynamic base transport correction factor is proposed to accurately capture the carrier transport behavior of parasitic transistors under high-injection conditions. The model analyzes the differences in carrier transport and recombination mechanisms under low-side (LS) and HS conditions and introduces a k-factor to dynamically modify the base transport coefficient. The k-factor accounts for the nonlinear widening of the effective base width and enhanced recombination under dual injection in HS conditions. Layout-dependent geometric parameters are also included in the model topology to quantify multi-finger current crowding and parasitic resistance, ensuring accurate current distribution in multi-finger LDMOS structures and improving scalability. Experimental validation on wafer-level LDMOS devices under diverse bias conditions shows that the model achieves RMS errors below 5% for key terminal currents (I_D, I_ISO, I_S), demonstrating significantly improved accuracy compared with the conventional GP model, which exhibits RMS errors exceeding 17% under HS conditions. In summary, the proposed SPICE compact model provides a physically based and scalable approach for accurately describing parasitic transistor behavior in junction-isolated LDMOS devices, enabling more accurate prediction of power loss, reverse-recovery behavior, and electrical stress for BCD power IC design.