A novel 4H-SiC MOSFET with asymmetric P-type implantation in the JFET region (AJPI-MOSFET) is proposed to improve the trade-off among on-state resistance, drain-induced barrier lowering (DIBL), and switching performance. By extending one P-well into only part of the JFET region, two laterally coupled local MOS branches sharing common source, gate, drain, and JFET/drift regions are formed. The short-channel MOS branch (MS) has a shorter effective channel and a wider current path, whereas the P-extended MOS branch (ME) has a longer effective channel and a higher threshold voltage. During turn-on, MS first establishes the main low-resistance current path, and ME subsequently participates in conduction as the gate voltage increases. Meanwhile, the reverse-biased P/N junction associated with ME expands its depletion region into the JFET region, redistributes the equipotential lines, and suppresses the penetration of the drain electric field toward the channel. The proposed structure therefore preserves conduction capability through MS while improving channel electrostatic control and reducing gate-drain coupling through ME. The influences of the P-type implantation coverage, depth, and concentration on the static and dynamic characteristics are investigated by two-dimensional TCAD simulations. The product of the on-state resistance (R_ON) and DIBL coefficient (k_DIBL), R_ON·k_DIBL, and the product of R_ON·and the Miller charge (Q_GD), R_ON·Q_GD, are employed to evaluate the conduction-DIBL trade-off and high-frequency performance, respectively. The optimized AJPI-MOSFET has a P-type JFET coverage ratio of 1/4, an implantation depth of 0.25 μm, and a doping concentration of 5×10¹⁶ cm^-3. Its R_ON and k_DIBL are 15.05 mΩ and 1.206 mV/V, respectively. Compared with the conventional vertical double-diffused MOSFET (VDMOS), the optimized device increases R_ON by only 1.5% while reducing k_DIBL by 17.2%. Compared with the center-PB MOSFET, it reduces R_ON by 7.3% while maintaining a comparable k_DIBL. Although the asymmetric electric-field distribution results in a lower breakdown voltage of 1497 V, the device still meets the 1200 V design target. The simulated conduction-band profiles show that the barrier lowerings in MS and ME are 18.45 and 12.63 meV, respectively, compared with 19.14 meV in the conventional VDMOS. The smaller barrier variation in ME confirms the electric-field protection provided by the asymmetric P-type region, while the current-density distributions verify the sequential establishment of the MS and ME current paths. The reduced gate-drain coupling also shortens the Miller-charge interval and improves the R_ON·Q_GD figure of merit. Under an 800 V bus voltage and a load current of approximately 33.3 A, the optimized AJPI-MOSFET exhibits EON and EOFF values of 266.84 and 166.22 μJ, respectively. Its ESW is 433.06 μJ, which is 2.0% and 2.1% lower than those of the conventional and center-PB MOSFET, respectively. These results demonstrate that asymmetric partial-width P-type implantation provides an effective approach to coordinating the low-resistance current path with the electric-field-control region, thereby improving the conduction-DIBL trade-off and switching performance of planar-gate 4H-SiC MOSFETs.