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中国物理学会期刊

面向后摩尔Ge-CMOS制造的超薄高介电常数LaLuO3栅介质工艺研究

CSTR: 32037.14.aps.74.20250126

Demonstration of ultra-thin high-k LaLuO3 gate dielectric for Ge-CMOS manufacture in More Moore application

CSTR: 32037.14.aps.74.20250126
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  • IV族元素锗材料由于具有电子和空穴迁移率高、禁带宽度小、与硅工艺相兼容等优势, 在低功耗高迁移率场效应晶体管领域具有广泛的应用潜力, 相应的Ge基金属-氧化物-半导体场效应晶体管(MOSFET)技术成为延续摩尔(more Moore)和超越摩尔(more than Moore)技术领域的前沿研究热点. 面向高迁移率的Ge基晶体管制备, 高质量栅极氧化物工艺是关键. 而高介电常数的Ge基栅极氧化物可以在提高栅控能力的同时, 有效降低器件栅极漏电, 提升器件的性能. 稀土系氧化物LaLuO3介电常数较高, 并且晶化温度高, 是制备Ge基MOSFET栅介质的优选方案. 本文通过磁控溅射技术制备Ge基氧化物LaLuO3介质, 并系统研究了退火工艺的气体种类、压强等氛围条件对Ge MOS栅电容特性的影响, 揭示了常压氧气氛围退火可以改善器件栅电容迟滞现象, 但存在栅界面层厚度增大的问题; 通过进一步发展基于高压低氧含量(0.1% O2)气体氛围退火技术, 在修复LaLuO3/Ge界面缺陷并减少氧空位产生的同时, 实现了极低的等效氧化层厚度(1.8 nm), 相应的LaLuO3/Ge MOS结构电容-电压曲线迟滞仅为 40 mV, 为Ge MOSFET提供了高性能LaLuO3/Ge栅极工艺方案.

     

    Germanium material holds great potential applications in low-power, high-mobility field-effect transistors because of their advantages of high electron and hole mobility, narrow bandgap, and compatibility with silicon CMOS technologies. The development of high-quality gate oxide processes is crucial in fabricating high-mobility Ge-based transistors, especially those with high dielectric constant for superior gate control and preferable gate stability. Rare-earth oxides represented by LaLuO3 have high dielectric constants and high crystallization temperatures, making them potential candidates for Ge-based metal-oxide-semiconductor field-effect transistor (MOSFET) gate technology. In this work, a germanium (Ge)-based oxide dielectric LaLuO3 is fabricated utilizing a p-type Ge substrate with a (111) crystal orientation and a doping concentration of 1×1016 cm–3, and radio-frequency (RF) co-sputtering 2-inch 99.9% La2O3 and Lu2O3 targets. Systematical investigations are conducted to evaluate the effects of annealing process conditions on the characteristics of the LaLuO3/Ge MOS gate structure under three specifically designed annealing atmospheres, i.e. nitrogen, oxygen, and a nitrogen-oxygen mixed gas with an N2:O2 ratio of 0.999∶0.001. Meanwhile, the influence of annealing pressure is also explored. The results show that annealing in pure oxygen at atmospheric pressure can reduce the hysteresis of gate capacitance, but it can lead to the formation of interface layers. Correspondingly, annealing technique based on high-pressure and low-oxygen-content (0.1% O2) atmosphere is developed, which not only improves the LaLuO3/Ge interface quality and suppresses the oxygen vacancy generation, but also achieves an extremely low equivalent oxide thickness (EOT) of 1.8 nm and a hysteresis voltage of only 40 mV, resulting in an ideal LaLuO3/Ge MOS structure. This work thus provides a high-performance LaLuO3/Ge gate process solution for Ge MOSFETs.

     

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