Ensuring on-orbit reliability of aerospace electronic systems requires effective radiation-hardened-by-design (RHBD) at the standard-cell level. This study addresses a less-studied single-event-upset (SEU) mechanism in a settable dual-interlocked storage-cell (DICE) flip-flop designed in SMIC 40 nm technology, which originates from its set-control path. A combined simulation approach integrates full-layout heavy-ion strike scanning using TREES with a 0.1 μm spatial grid and SPICE transient analysis driven by TCAD-calibrated single-event-transient (SET) current injection, thereby correlating layout-sensitive regions with circuit-critical nodes. Results indicate that heavy-ion strikes with a linear energy transfer (LET) of 37 MeV·cm²·mg^–1 on the drain regions of set-circuit transistors P1 and N2 generate characteristic “101”-type SET pulses. Under the critical input condition where the data input D is at logic low and the set input SD is at logic high, these pulses transiently activate the normally-off set path, forcing the output Q from low to high and triggering SEU. To mitigate this vulnerability, we propose a set-redundancy RHBD scheme that utilizes two physically separated set-signal paths. The layout spacing minimizes the probability of concurrent transients, while the inherent self-recovery of the DICE core corrects single-node voltage deviations. Post-RHBD simulations show no SEU events under the tested conditions: the SEU cross-section drops from 1.7×10^–9 cm² in the baseline design, corresponding to 18 events out of 1691 strike locations, to zero in the RHBD version with 0 events out of 1919 strike locations. The introduced overhead remains moderate, with a 14.3% area increase and a 14.5% power increase, while critical timing parameters are largely unaffected. This work provides a concrete RHBD strategy and a correlated simulation framework for identifying and hardening latent weak points in radiation-hardened standard cells for aerospace integrated circuits.