Single event burnout (SEB) is a critical reliability concern for GaN high-electron-mobility transistors (GaN HEMTs) intended for space power applications. While SEB currents reported in the literature are typically characterized by an abrupt transition into a destructive high-current state (“direct burnout”), a step current evolution has also been sporadically observed but remains poorly understood. In this work, we investigate the physical origin of the step SEB current by combining femtosecond pulsed laser single event effect experiments, capacitance-controlled comparative tests, and TCAD simulations on two commercial enhancement-mode GaN HEMTs (INN650D150A and EPC2034C). Experiments were performed using a 35 fs, 630 nm laser at 5 kHz repetition rate and 9 nJ pulse energy, under off-state bias (V_G = V_S = 0 V) with drain bias stepped until failure. Distinct SEB signatures were reproducibly identified: INN650D150A exhibited a direct transition to the compliance-limited current at V_DS = 400 V, whereas EPC2034C showed a step current waveform at V_DS = 150 V, featuring an initial stable plateau followed by a rapid rise into the destructive regime. Electrical characterization revealed that EPC2034C possesses substantially larger intrinsic parasitic capacitances (C_GS and C_DS) than INN650D150A, motivating a capacitance-driven hypothesis for the step behavior. To verify this hypothesis, a set of external capacitance experiments was conducted on INN650D150A. The step SEB current was not observed when only the drain-side or gate-side capacitance was increased, nor when both sides were increased with insufficient capacitance. In contrast, a clear step response was triggered only when both drain and gate were simultaneously shunted by large capacitors (C_DS,ext = 680 pF and C_GS,ext = 1 nF), producing a stable plateau current (~6.5 μA) before final burnout, and concurrently reducing the SEB threshold voltage. The analysis indicates that during the triggering of the single event effect, the drain current undergoes a transient increase, while the rapid charging of the capacitances at the drain and gate limits the further transient rise of the current. Subsequently, during the process in which no additional single event effect is triggered, the drain current remains nearly constant, thereby giving rise to the observed step current. Finally, TCAD simulations were employed to clarify how enhanced parasitic capacitance can also lower the SEB threshold voltage. Two capacitance-enhanced device variants (CE1-HEMT/CE2-HEMT) were constructed by reducing the thickness of the Si₃N₄ passivation layer relative to a baseline p-GaN gate structure. Electrons generated by heavy ion irradiation drift toward the drain under the applied electric field. The increase in parasitic capacitance leads to a higher electron concentration near the drain and enhances electron trapping, which promotes negative charge accumulation near the drain. Consequently, the local electric field is intensified, reducing the SEB threshold voltage. The experimental evidence and simulation results demonstrate that parasitic capacitance is a decisive factor governing both the shape of the SEB current (direct vs. step) and the SEB threshold voltage, providing practical guidance for radiation-hard design.