In this paper, we propose a novel scheme to mitigate z-direction interference (Z-interference) in charge-trap-based 3D NAND flash memory. Our approach reduces the electric field (E-field) in the inter-cell region of the charge trapping layer during programming aggressor (Agr) cell by increasing the trapped electrons concentration of the charge-trapping layer in the inter-cell region. Specifically, prior to programming the Agr cell, alternate erase and soft program operation is employed to introduce a significant number of electrons into the inter-cell region. We validate our proposed scheme using both technology computer-aided design (TCAD) simulation and experimental measurements. The experimental results show that the proposed scheme achieves a 14.62% reduction compared to the conventional method. Besides, as the cell size of 3D NAND flash memory continues to scale down, the proposed scheme exhibits a more pronounced suppression effect on Z-interference. Using this approach can improve 3D NAND Flash reliability.