In fact, electrostatic discharge (ESD) events tend to accompany the entire lifetime of semiconductor devices. Compared with conventional depletion-mode devices, the complex gate structure of enhancement-mode p-GaN gate AlGaN/GaN high-electron-mobility transistors (HEMTs) may make them more sensitive to ESD events. In this work, the effects of forward gate-drain and drain-source ESD stress under the human body model (HBM) on the electrical characteristics and trap evolution of p-GaN gate AlGaN/GaN HEMTs are investigated. Meanwhile, combining the low-frequency noise and frequency-dependent conductance techniques, the intrinsic relationship between changes in electrical parameters and the evolution of trap parameters was carefully discussed. It is found that under forward gate-drain and drain-source ESD stresses, the ESD failure thresholds of the p-GaN gate AlGaN/GaN HEMTs are 7400 V and >8000 V (The maximum output voltage of the ESD simulator is 8000V), respectively. Compared with other electrical parameters, the saturation drain current degrades first under both ESD stress conditions. When the forward gate-drain ESD stress voltage increased to 7500V, besides the saturation drain current, the degradation in threshold voltage, peak transconductance, and gate leakage current are also observed. After the 7500 V forward gate-drain ESD stress, the saturation drain current decreases by 17.32%, the threshold voltage shifts positively by 0.13V, the peak transconductance decreases by 10.23%, and the gate leakage current increases by approximately one order of magnitude (at V_GS = 6V). The positive drain-source ESD stress experiment results show that even when the stress voltage reaches the maximum output voltage of the ESD simulator (8000V), there are no significant changes in the electrical and trap characteristics of the p-GaN gate AlGaN/GaN HEMTs. With the increase in the number of stress cycles, only the degradation in saturation drain current is gradually observed. After 50 times 8000V positive drain-source ESD stress, the saturation drain current decreases by 7.96%. The measurement results of the low-frequency noise and frequency-dependent conductance techniques indicate that both types of ESD stresses first damage the region near the channel. The greater the ESD stress voltage, the higher the trap density generated near the device channel, which is consistent with the degradation trend of the saturation drain current. As the voltage increases to 7500 V, forward gate-drain ESD stress will further induce traps at the p-GaN/AlGaN interface, which is consistent with the degradation of the threshold voltage and gate leakage current. It is believed that the traps generated near the channel by the two types of ESD stresses dominate the degradation of the saturation drain current. The increase in p-GaN/AlGaN interface traps after 7500 V forward gate-drain ESD stress dominates the positive shift of the threshold voltage and the increase in gate leakage current. Based on the experimental results, this paper also presents three suggestions for improving the ESD tolerance of p-GaN gate AlGaN/GaN HEMTs. This work can provide support for the ESD robust design and failure analysis of the p-GaN gate AlGaN/GaN HEMTs.