Resistive random access memory (RRAM) has emerged as a promising candidate for high-density data storage in the post-Moore era, owing to its simple structure, excellent CMOS compatibility, and potential for in-memory computing. However, conventional two-dimensional RRAM based on the 1T1R (one-transistor–one-resistor) architecture faces fundamental scaling limitations, mainly due to the trade-off between operating current and transistor footprint, which constrains further density improvement. This paper reviews recent progress in high-density RRAM, focusing on key bottlenecks in two-dimensional scaling and the transition toward three-dimensional integration. The evolution of 1T1R structures and optimization strategies for nTmR array configurations are analyzed at both device and array levels, with attention to challenges including insufficient driving capability, aggravated sneak-path interference, and reliability degradation. Recent progress in three-dimensional RRAM is then discussed, focusing on the switching mechanisms and performance requirements of selector devices. Representative technologies, including metallic filament-based selectors, amorphous chalcogenide threshold switching devices, and insulator-metal transition selectors, are compared. The advantages of self-selective memory cells for density enhancement are also discussed. At the array level, horizontal stacking, vertical stacking, and transistor-based three-dimensional architectures are compared, among which vertical stacking is identified as the most promising approach for ultra-high-density integration. Key issues in three-dimensional arrays, including leakage paths, parasitic effects, and thermal management, are analyzed along with potential solutions. Overall, improving selector performance and optimizing three-dimensional stacking architectures are critical for achieving ultra-high-density RRAM, supporting next-generation non-volatile memory and intelligent computing systems.