An analytical trapping modle, which utilizes concise parameters to describe the impact of deep level traps in the p-buffer layer on the output characteristics, is proposed for 4H-SiC RF power MESFET. This model is simple in calculations compared with normally used 2D numerical model. It also takes into account the self-heating effect that plays an important role in saturated region of I-V characteristics. The description of transconductance degradation, drain conductance decrease and pinch-off voltage dispersion caused by the traps is easily derived by theoretical analysis. The result shows good agreement between simulations and measurements.