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中国物理学会期刊

栅介质形貌调控MoS2应变及其晶体管性能

Strain engineering in MoS2 transistors via topography modulation of the dielectric

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  • 硅基电子器件极大推动了半导体产业发展, 但随着特征尺寸微缩已接近物理极限, 短沟道效应和散热问题日益严峻. 二维过渡金属硫族化合物(transition-metal dichalcogenides, TMDCs)因具有原子层厚度及优异性能被视为潜在替代材料. 单层二硫化钼(molybdenum disulfide, MoS2)薄膜晶体管理论迁移率高达420 cm2/(V·s), 但其原子级薄的厚度易受界面散射影响, 实验测量的室温迁移率始终低于理论值. 研究表明应变工程是提升迁移率的有效方法, 拉伸应变可减小MoS2带隙和载流子有效质量, 从而提高迁移率. 本工作提出了一种利用栅介质形貌调控方法来局部调控MoS2晶体管中的应力, 从而研究MoS2晶体管性能会受到的影响. 利用具有通孔结构的超薄多孔阳极氧化铝(anodic aluminum oxide, AAO)在衬底预沉积10 nm Au纳米圆台, 随后通过原子层沉积(atomic layer deposition, ALD)保形生长栅介质. 在转移MoS2薄膜后, 利用栅介质表面凸起结构对MoS2施加0.56%的拉伸应变, 但MoS2晶体管迁移率并未得到理想的提升(仅3倍). 扫描电子显微镜(scanning electron microscope, SEM)和变温电学测试证明纳米圆台结构引入拉伸应变的同时也引入了微观褶皱, 增强了MoS2中声子散射从而降低迁移率. 本研究初步阐明了局部应力调控与微观褶皱对MoS2晶体管电学输运机制的综合影响, 为后续二维半导体晶体管的应变工程研究提供了重要的实验参考.

     

    Silicon-based field effect transistors have significantly driven the development of the semiconductor industry, but the scaling of feature sizes is approaching physical limits, short-channel effects and thermal dissipation issues have become increasingly severe. Two-dimensional transition metal dichalcogenides (TMDCs) are regarded as a potential alternative channel material for ultimate transistor scaling, owing to their atomically thin thickness and superior properties. Molybdenum disulfide (MoS2) transistors theoretically exhibit a mobility of up to 420 cm2/(V·s), but their atomically thin thickness makes them susceptible to interface scattering, resulting in experimentally measured room-temperature mobility values below theoretical values. Strain engineering is an effective method to enhance mobility—tensile strain can reduce the bandgap and carrier effective mass of MoS2, thereby improving mobility. This study proposes a method to regulate the local strain in MoS2 transistors by modulating the gate dielectric topography, and investigates the resulting effects on the performance of MoS2 transistors. We utilize an ultrathin porous nanotemplate anodic aluminum oxide (AAO) with via-structures to predeposit 10 nm Au truncated-nanocones on the substrate, followed by a conformal deposition of the gate dielectric through atomic layer deposition (ALD). After transferring MoS2 film, the truncated-nanocone structures of the gate dielectric topography successfully apply a 0.56% tensile strain to MoS2. However, the mobility of truncated-nanocone-structure- based MoS2 transistors does not achieve the desired ideal improvement (only 3-fold increase). Scanning electron microscopy (SEM) and temperature-dependent electrical measurements reveal that while the truncated-nanocone structures introduce tensile strain, they simultaneously induce microscopic wrinkles, which consequently enhance phonon scattering in MoS2 and reduce the transistor mobility. This study preliminarily elucidates the combined effects of local strain regulation and microscopic wrinkles on the electrical transport mechanism of MoS2 transistors, offering an important experimental reference for future strain engineering research in two-dimensional semiconductor-based transistors.

     

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