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中国物理学会期刊

空腔嵌入绝缘体上硅衬底制备技术

CSTR: 32037.14.aps.72.20230198

Fabrication technology of void embedded silicon-on-insulator substrate

CSTR: 32037.14.aps.72.20230198
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  • 空腔嵌入绝缘体上硅(void embedded silicon on insulator, VESOI)衬底是一种面向新型互补金属氧化物半导体(complementary metal oxide semiconductor, CMOS)器件及集成技术的新型SOI衬底材料. 当采用离子剥离技术制备该衬底时, 由氢气形成的板状气泡会聚集在衬底剥离界面, 对空腔结构产生挤压作用, 并有可能造成空腔结构的破损, 因而有必要对VESOI衬底制备过程中的应力机制和工艺稳定性进行深入研究. 本文以单个矩形空腔结构为研究对象, 借助固支梁理论分析了其在工艺制备过程中的力学状态, 并利用有限元工具构建了其三维几何模型. 通过应力仿真, 找到了该空腔结构的破裂失效原因, 并确认了其脆弱位点. 结果表明, 矩形空腔结构短边长度w、顶硅薄膜厚度t以及氢气泡压力是影响顶硅薄膜应力状态的主要因素. 当w/t值超过4—5时, 硅薄膜将因应力过大而破裂, 破裂位点分布于空腔结构长边方向. 通过优化顶层硅厚度t, 以及内嵌空腔结构、尺寸, 本工作成功制备了符合CMOS产线要求的高质量8 in (1 in = 2.54 cm) VESOI衬底. 该工作对基于VESOI衬底的集成技术具有较好参考价值.

     

    Void embedded silicon-on-insulator (VESOI) substrate is a newly developed silicon-on-insulator (SOI) substrate for advanced complementary metal oxide semiconductor (CMOS) devices and integration technology. However, in the ion-cutting process for preparing the substrate, numerous hydrogen bubbles aggregate at the cut interface, which compresses the cavity structure and might cause the thin film above the cavity to be damaged and delaminated. Therefore, it is necessary to conduct in-depth research on the stress mechanism and process stability in the preparation of VESOI substrates. This study focuses on a single rectangular cavity structure and uses the fixed-supported beam theory to analyze its mechanical behavior during fabrication, and a three-dimensional model of cavity structure is constructed by using the finite element analysis tool. Through stress simulation, the failure mechanism of the cavity structure is identified, and the weak points are confirmed. The results show that the short side length (w), top silicon film thickness (t), and hydrogen bubble pressure are the main factors affecting the stress state of the top silicon film. When the w/t ratio exceeds 4–5, the silicon film will fracture owing to excessive tensile stress, and the fracture site is along the long side of the rectangular cavity. By increasing the thickness of the top silicon film slightly and adding support structures inside the cavity (to reduce w), this work successfully prepares high-quality 8-inch VESOI substrates that meet the requirements for the CMOS production line. The present study is expected to provide valuable idea for the development of integrated technologies relying on VESOI substrates.

     

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