Spin-orbit torque magnetic random-access memory (SOT-MRAM) possesses high speed, ultrahigh endurance and excellent compatibility with advanced semiconductor manufacturing processes, and is considered to be a promising non-volatile memory technology. However, the free layer in the magnetic tunnel junction (MTJ) is affected by an intrinsic bias field (H_s) originating from the stray field of reference layer and interlayer coupling associated with surface roughness. The bias field gives rise to a pronounced asymmetry in the critical current density for magnetization switching between the two resistance states, thereby increasing the overall energy consumption. Recent solutions typically introduce additional magnetic layers within the MTJ stack to compensate for H_s. However, such an approach increases manufacturing costs and limits their practicality in wafer-scale manufacturing. To address the issue of asymmetry, we propose a method that avoids modifying the original MTJ stack. The basic idea is to regulate the write current via local stray magnetic field engineering, which involves filling magnetic materials into designated vertical interconnect access (VIA) channels during the back-end-of-line (BEOL) process. Taking the well-studied perpendicular magnetic anisotropy (PMA) SOT-MTJ as an example, where the undesired H_s is typically oriented along the z-axis, micromagnetic simulations show that inserting an in-plane ferromagnetic layer can significantly reduce the write-current asymmetry and provide the auxiliary field for deterministic switching as well. Furthermore, by slightly shifting the MTJ away from its original centered position, the bias-compensation effect can be further optimized, reducing the write-current bias ratio from 21.6% in the conventional design to 1.3%. Notably, this approach implements field-free switching—a critical feature for SOT-MTJ applications targeting high integration density. The concept is also applicable for SOT-MTJs with in-plane magnetic anisotropy. Finally, the down-scaling analyses demonstrate excellent compatibility: even when scaled at 20% of the original size (MTJ diameter ≈ 10 nm), the write-current bias ratio remains at a low level of 0.1%, indicating that our design is effective across MTJs and highly suitable for high-density integration with advanced technology nodes.