The development of high-performance GaN-based p-FETs (p-type field effect transistors) is critical for enabling monolithic complementary integration in all-GaN power systems, yet their progress is hindered by poor on/off current ratios (~10²) due to the difficulty in depleting the two-dimensional hole gas (2DHG) channel. While recessed-gate structures fabricated by dry etching can improve the switching ratio to ~10⁵, they introduce interface damage and threshold voltage hysteresis (ΔV_TH). Subsequent repair techniques, such as NMP solution treatment or oxygen/hydrogen plasma processing, partially mitigate these issues but still suffer from suboptimal subthreshold swing, ΔV_TH, and added process complexity. Further improvements are needed to achieve robust, high switching ratio p-FETs without excessive post-processing.

To address this issue, this paper designs and fabricates a slanted-channel GaN-based p-FET that eliminates the need for etching the p-GaN layer under the gate. Unlike conventional p-FETs that rely on precise etching of the p-GaN layer to achieve channel pinch-off, semipolar gate structure enables depletion region extension to the 2DHG channel under zero gate bias by weakening polarization-induced ionization of acceptor impurities. This mechanism facilitates effective channel pinch-off without aggressive etching, offering a new pathway to achieve high switching ratios in GaN p-FETs.

The fabricated device achieves excellent switching characteristics (I_on/I_off = 4.3×10⁶) and a low subthreshold swing (SS = 157 mV/dec). Since the fabrication process avoids etching the p-GaN channel layer, the dielectric/channel layer interface exhibits a low interface state density (approximately 1.61×10¹² cm^–2·eV^–1), resulting in excellent device stability under gate bias stress and temperature variations. This structure provides an innovative pathway for advancing the performance of GaN-based p-FETs.