Electro-static discharge failure analysis and design optimization of gate-driver on array circuit in InGaZnO thin film transistor backplane

Ma Qun-Gang; Zhou Liu-Fei; Yu Yue; Ma Guo-Yong; Zhang Sheng-Dong

doi:10.7498/aps.68.20190265

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Ma Qun-Gang, Zhou Liu-Fei, Yu Yue, Ma Guo-Yong, Zhang Sheng-Dong. Electro-static discharge failure analysis and design optimization of gate-driver on array circuit in InGaZnO thin film transistor backplaneJ. Acta Physica Sinica, 2019, 68(10): 108501. DOI: 10.7498/aps.68.20190265

Citation:

Ma Qun-Gang, Zhou Liu-Fei, Yu Yue, Ma Guo-Yong, Zhang Sheng-Dong. Electro-static discharge failure analysis and design optimization of gate-driver on array circuit in InGaZnO thin film transistor backplaneJ. Acta Physica Sinica, 2019, 68(10): 108501. DOI: 10.7498/aps.68.20190265

Citation:

Ma Qun-Gang, Zhou Liu-Fei, Yu Yue, Ma Guo-Yong, Zhang Sheng-Dong. Electro-static discharge failure analysis and design optimization of gate-driver on array circuit in InGaZnO thin film transistor backplaneJ. Acta Physica Sinica, 2019, 68(10): 108501. DOI: 10.7498/aps.68.20190265