One-step-annealing-process constructed WSe<sub>2</sub> complementary transistors

CUI Xinyu; SHAN Junjie; SUN Xiaoyu; PAN Chen; SUN Jiameng; YU Wentao; LIANG Shijun; MIAO Feng

doi:10.7498/aps.74.20250648

Abstract

Two-dimensional (2D) semiconductor materials exhibit tremendous potential for post-Moore integrated circuits due to their unique physical properties and superior electrical characteristics. However, critical challenges in polarity modulation and complementary integration have significantly hindered the practical applications of 2D materials. The development of compatible polarity-modulation techniques has emerged as a critical step in achieving device functional integration for constructing 2D materials-based complementary circuits. This study innovatively proposes a one-step-annealing-driven polarity-modulation strategy for 2D semiconductors. It is demonstrated in this study that the conduction behavior of Pd-contacted WSe₂ transistors transitions from n-type to p-type dominance after annealing, while Cr-contacted devices maintain n-type dominance. Based on this polarity-modulation strategy, by selectively fabricating source and drain electrodes with different metal materials (Pd and Cr) on the same WSe₂, combined with a one-step annealing process, the monolithic integration of complementary transistors is achieved, thereby realizing inverter function through device interconnection. The fabricated inverters exhibit a high voltage gain of 23 and a total noise margin of 2.3 V(0.92 V_dd) at an applied V_dd of 2.5 V. This work not only establishes a novel technical pathway for polarity modulation in 2D materials but also provides crucial technological support for developing 2D semiconductor-based complementary logic circuits.

Keywords:

Authors and contacts

1.
National Laboratory of Solid State Microstructures, School of Physics, Nanjing University, Nanjing 210093, China
2.
Key Laboratory of State Manipulation and Advanced Materials in Provincial Universities, School of Physics and Technology, Nanjing Normal University, Nanjing 210023, China
3.
Institute of Interdisciplinary Physical Sciences, School of Physics, Nanjing University of Science and Technology, Nanjing 210094, China

Corresponding author: SHAN Junjie, junjieshan@njnu.edu.cn ; PAN Chen, chenpan@njust.edu.cn ; LIANG Shijun, sjliang@nju.edu.cn ;

Funds: Project supported by the National Key R&D Program of China (Grant Nos. 2022YFA1402500, 2023YFF1203600), the National Natural Science Foundation of China (Grant Nos. 62122036, 62034004, 61921005, 62204112), and the Natural Science Foundation of Jiangsu Province, China (Grant No. BK20220774).

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References

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Cited By

图 1 WSe₂ FETs的极性调控　(a) 以Pd和Cr作为源漏接触电极的WSe₂器件在退火前后的光学照片对比, 其中将退火前后Pd-WSe₂与Cr-WSe₂器件电极近邻沟道区域分别标记为区域Ⅰ, Ⅱ, Ⅲ和Ⅳ, 比例尺为1 μm; (b) 图(a)中对应区域“Ⅰ—Ⅳ”的拉曼光谱表征结果; 以Pd(c)和Cr(d)为源漏接触电极的背栅结构WSe₂ FETs退火前后的转移特性曲线, 施加V_ds为3 V, 器件结构示意图如插图所示

Figure 1. Polarity modulation of WSe₂ FETs: (a) Comparative optical micrographs of Pd-contact and Cr-contact WSe₂ devices before and after annealing. The electrode-proximal channel zones in Pd-WSe₂ and Cr-WSe₂ devices are labeled as regions Ⅰ, Ⅱ, Ⅲ and Ⅳ before and after annealing states, respectively, the scale bar is 1 μm. (b) Raman spectrum characterization results of the corresponding regions “Ⅰ–Ⅳ” marked in Figure (a). Transfer characteristic curves of back-gated WSe₂ FETs with Pd contact (c) and Cr contact (d) before and after annealing, measured at V_ds of 3 V, and the insets illustrate the schematics of device structures.

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图 2 基于WSe₂的互补FETs的单片集成与电学特性　(a) 在单一WSe₂材料上集成互补FETs的器件结构示意图, 经退火操作后, Pd-WSe₂ FET表现为p-FET, Cr-WSe₂ FET表现为n-FET; (b) p-FET和n-FET的转移特性曲线, 其中红色曲线代表p-FET, 蓝色曲线代表n-FET, 施加的V_ds分别为–1 V和1 V; p-FET(c)和n-FET(d)的输出特性曲线, V_g变化范围为0—2.5 V, 变化步长为0.5 V, 施加的V_s分别为3和0 V

Figure 2. Monolithic integration and electrical characteristics of WSe₂-based complementary FETs: (a) Schematic of the integrated complementary FETs on a single WSe₂ flake, the annealed Pd-WSe₂ FET serves as p-FET and the Cr-WSe₂ FET functions as n-FET; (b) transfer characteristic curves of the p-FET (red curve) and n-FET (blue curve), the applied V_ds are –1 V and 1 V, respectively; output characteristic curves of the p-FET (c) and n-FET (d), the V_g swept from 0 to 2.5 V with step increments of 0.5 V, and the applied V_s are 3 and 0 V, respectively.

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图 3 基于WSe₂ FETs构建的互补逻辑反相器及其电学性能　(a) p-FET和n-FET串联组成的互补逻辑反相器的电路图; (b) 反相器的电压传输特性曲线, 所施V_dd范围为1—2.5 V, 变化步长为0.5 V; (c) 基于反相器电压传输特性曲线提取的电压增益; (d) 当V_dd为2.5 V时, WSe₂反相器的蝶形电压传输特性曲线

Figure 3. Construction and electrical characteristics of complementary logic inverter based on WSe₂ FETs: (a) Circuit diagram of the complementary logic inverter composed of p-FET and n-FET connected in series; (b) voltage transfer characteristic curves of inverter, the applied V_dd range from 1 to 2.5 V with step increments of 0.5 V; (c) voltage gain extracted from the voltage transfer characteristic curves of the inverter; (d) butterfly voltage transfer characteristic curves of WSe₂ inverter at applied V_dd of 2.5 V.

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One-step-annealing-process constructed WSe₂ complementary transistors

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Corresponding author: SHAN Junjie, junjieshan@njnu.edu.cn ; PAN Chen, chenpan@njust.edu.cn ; LIANG Shijun, sjliang@nju.edu.cn ;

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One-step-annealing-process constructed WSe2 complementary transistors

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Corresponding author: SHAN Junjie, junjieshan@njnu.edu.cn ; PAN Chen, chenpan@njust.edu.cn ; LIANG Shijun, sjliang@nju.edu.cn ;

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One-step-annealing-process constructed WSe₂ complementary transistors