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Capacitance characteristics of atomic layer deposited Al2O3/n-GaN MOS structure

Yan Da-Wei Li Li-Sha Jiao Jin-Ping Huang Hong-Juan Ren Jian Gu Xiao-Feng

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Capacitance characteristics of atomic layer deposited Al2O3/n-GaN MOS structure

Yan Da-Wei, Li Li-Sha, Jiao Jin-Ping, Huang Hong-Juan, Ren Jian, Gu Xiao-Feng
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  • The Ni/Au/Al2O3/n-GaN metal-oxide-semiconductor structure with circular transparent electrode has been fabricated by using atomic layer deposition technique. Effects of ultra-violet (UV) light illumination on the capacitance characteristics and deep interface states are analyzed. Physical origin of bias-induced capacitance drop in the accumulation region of some non-ideal devices is explored. Due to the extremely long electron emission time and the extremely slow minority carrier generation rate, a typical deep depletion behavior can be observed in the dark room-temperature capacitance-voltage sweep curve, and the deep-level interface state occupancy above the electron quasi-Fermi level remains unchanged. Under the UV illumination, photo-induced holes will empty the deep interface traps above the electron quasi-Fermi level, and also de-charge the deep donor-like traps in the oxide layer. The anomalous capacitance drop in the accumulation region is attributed to the bias-dependent excessive leakage conductance across the dielectric layer, which might be induced by a charge-to-breakdown process related to electrical traps in the oxide and the inferior interface quality.
    • Funds: Project supported by the National Natural Science Foundation of China (Grant No. 11074280), the Natural Science Foundation of Jiangsu Province, China (Grant No. BK2012110), the Fundamental Research Funds for the Central Universities, China (Grant Nos. JUSRP51323B, JUDCF13038), PAPD of Jiangsu Higher Education Institutions, the Summit of the Six Top Talents Program of Jiangsu Province, China (Grant No. DZXX-053), and the Graduate Student Innovation Program for University of Jiangsu Province (Grant No. CXLX13-740).
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    Higashiwaki M, Matsui T, Mimura T 2006 IEEE Electron Device Lett. 27 16

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    Sze M, Ng K K 2006 Physics of semiconductor devices New York: Wiley 209

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    Muller R S, Kamins T I 1986 Device Electrons for Interated Circuits New York: Wiley 443

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  • [1]

    Kohm E, Daumiller I, Schmid P, Nguyen N X, Nguyen C N 1988 Electron. Lett. 35 1022

    [2]

    Kumar V, Lu W, Schwindt R, Kuliev A, Simin G, Yang J, Khan M A, Adesida I 2001 IEEE Electron Device Lett. 48 465

    [3]

    Rumyantsey S L, Pala N, Shur M S, Borovitskaya E, Dmitriew A P, Levinshtein M E, Gaska R, Khan M A, Yang J W, Hu X H, Simin G 2001 IEEE Trans. Electron Devices 48 530

    [4]

    Koley G, Tilak V, Eastman L F, Spencer M G 2003 Electron. Lett. 50 886

    [5]

    Kim H, Thompson R M, Tilak V, Prunty T R, Shealy J R, Eastman L F 2003 IEEE Electron Device Lett. 24 421

    [6]

    Green B M, Chu K K, Chumbes E M, Smart J A, Shealy J R Eastman L F 2002 IEEE Electron Device Lett. 21 268

    [7]

    vertiatchikh A, Eastman L F, Schaff W J, Prunty I 2002 Electron. Lett. 38 388

    [8]

    Edwards A P, Mittereder J A, Binari S C, Katzer D S, Storm D F, Roussos J A 2005 IEEE Electron Device Lett. 26 225

    [9]

    Lee J S, Vescan A, Wieszt A, Dietrich R, Leier H, Kwon Y S 2002 Electron. Lett. 37 130

    [10]

    Higashiwaki M, Matsui T, Mimura T 2006 IEEE Electron Device Lett. 27 16

    [11]

    Sze M, Ng K K 2006 Physics of semiconductor devices New York: Wiley 209

    [12]

    Muller R S, Kamins T I 1986 Device Electrons for Interated Circuits New York: Wiley 443

    [13]

    Wolters D R, Van J J 1985 Philips J. Res. 40 115

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Publishing process
  • Received Date:  06 April 2013
  • Accepted Date:  04 July 2013
  • Published Online:  05 October 2013

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