Search

Article

x

留言板

尊敬的读者、作者、审稿人, 关于本刊的投稿、审稿、编辑和出版的任何问题, 您可以本页添加留言。我们将尽快给您答复。谢谢您的支持!

姓名
邮箱
手机号码
标题
留言内容
验证码

Through-silicon-via-aware interconnect prediction model for 3D integrated circuirt

Qian Li-Bo Zhu Zhang-Ming Yang Yin-Tang

Through-silicon-via-aware interconnect prediction model for 3D integrated circuirt

Qian Li-Bo, Zhu Zhang-Ming, Yang Yin-Tang
PDF
Get Citation

(PLEASE TRANSLATE TO ENGLISH

BY GOOGLE TRANSLATE IF NEEDED.)

Metrics
  • Abstract views:  2356
  • PDF Downloads:  719
  • Cited By: 0
Publishing process
  • Received Date:  26 May 2011
  • Accepted Date:  11 July 2011
  • Published Online:  05 March 2012

Through-silicon-via-aware interconnect prediction model for 3D integrated circuirt

    Corresponding author: Zhu Zhang-Ming, zmyh@263.net
  • 1. School of Microelectronics, Xidian University, Xi’an 710071, China
Fund Project:  Project supported by the National Natural Science Foundation of China (Grant Nos. 60725415, 60676009), and the National Science and Technology Major Project of the Ministry of Science and Technology of China (Grant No. 2009ZX01034-002-001-005).

Abstract: Through-silicon-via (TSV) is one of the major design techniques in three- dimensional integrated circuit (3D IC). Based on the parasitic parameter extraction model, the parasitic resistance-capacitance (RC) parameters for different size TSVs are acquired and validated with Q3D simulation data. Using the results of this model, closed-form delay and power consumption expressions for buffered interconnect used in 3D IC are presented. Comparative results with 3D net without TSV in various cases show that TSV RC effect has a huge influence on delay and power of 3D IC, which leads maximum delay and power comsumption to extra increase 10% and 21\% on average, respectively. It is crucial to correctly establish a TSV-aware 3D interconnect model in 3D IC front-end design.

Reference (38)

Catalog

    /

    返回文章
    返回