Research progress of silicon and germanium quantum computing materials

Zhang Jie-Yin; Gao Fei; Zhang Jian-Jun

doi:10.7498/aps.70.20211492

Abstract

Semiconductor quantum dot is one of the promising ways to realize solid-state quantum computing. The key is to obtain high-quality semiconductor quantum computing materials. Silicon and germanium can be isotopically purified to achieve nuclear spin-free isotopes, meeting the requirement for long decoherence time. They are also compatible with the current CMOS technology, thus making them ideal material platforms for large scale integration. This review first summarizes the important progress of semiconductor quantum-dot quantum computing in recent years, then focuses on the material progress including the silicon-based Si/SiGe heterostructures, Ge/SiGe heterostructures, and Ge/Si one-dimensional wires, finally presents the outlook about the development of silicon and Ge quantum computing materials.

Keywords:

Authors and contacts

Key Laboratory of Nanophysics and Devices, Institute of Physics, Chinese Academy of Sciences, Beijing 100190, China

Corresponding author: Zhang Jian-Jun, jjzhang@iphy.ac.cn

Funds: Project supported by the National Key R&D Program of China (Grant No. 2016YFA0301701)

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图 1 (a) Si/SiGe异质结二维电子气低温霍尔峰值迁移率的发展, 其中实心圆圈和实心方块分别代表掺杂型结构和非掺杂型结构; 黑色、红色和蓝色分别代表SiGe缓冲层固定锗含量、Si/SiGe超晶格和组分渐变等3种不同生长方法; 插图是SiGe/Si/SiGe 异质结结构和能带结构对准示意图; (b)穿透位错密度对电子迁移率的影响^[64]; (c)应变硅层厚度对电子低温峰值迁移率的影响^[64]; (d) SiGe间隔层厚度对电子迁移率的影响^[68]

Figure 1. (a) Mobility of Si two-dimensional electron gas with time. Solid squares and circles refer to undoped structure and doped structure, respectively. The black, red and blue color refer to three different growth methods (constant Ge composition, Si/SiGe superlattice and the graded Ge composition). Inset images show the SiGe/Si/SiGe heterostructures and the schematic band-edge profile. (b) Effect of threading dislocations on electron mobility^[64]. (c) Effect of Si-channel thickness on electron mobility^[64]. (d) Effect of the spacer layer thickness on electron mobility^[68].

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图 2 (a)不同时期的Ge/SiGe异质结二维空穴气低温霍尔峰值迁移率, 其中实心圆圈和实心方块分别代表掺杂型结构和非掺杂型结构; 黑色、蓝色和红色分别代表SiGe缓冲层固定锗含量、组分正渐变和组分逆渐变等3种不同生长方法^[84]; (b) Ge衬底上固定锗组分生长SiGe缓冲层的截面TEM, 可看到在缓冲层及量子阱层产生大量堆垛层错^[92]; (c) Si衬底上锗组分逆渐变方法生长的Ge/SiGe空穴气结构的截面TEM图^[102], 位错主要分布在逆渐变缓冲层

Figure 2. (a) Improvement of two-dimensional hole gas low temperature Hall mobility of Ge/SiGe heterostructure with time. Solid squares and circles refer to undoped structure and doped structure. The black, blue and red color refer to three different growth methods (the constant Ge composition, forward grading and the reverse grading) ^[84]. (b) Cross-sectional TEM of SiGe buffer layer with constant Ge composition on Ge substrate, plenty of stacking faults inside the constant Ge composition buffer layer and Ge quantum well^[92]. (c) Cross-sectional TEM of two-dimensional hole gas obtained by reverse grading method^[102]. Dislocations are mainly localized inside the reverse grading buffer layer.

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图 3 (a) VLS方法生长纳米线的示意图; (b) VLS方法生长的Ge纳米线的TEM图^[104]; (c)结合激光烧蚀技术和VLS生长方法制备的直径为(5 ± 0.6) nm的Ge纳米线的TEM图^[47]; (d) Ge/Si核/壳纳米线的TEM图, 其中黑色部分为Ge核, 浅灰色部分为Si壳^[105]; (e) Ge/Si核/壳纳米线的高分辨TEM图, 表明Si壳为单晶结构^[105]; (f) Ge/Si核/壳纳米线的横截面示意图以及能带偏移示意图^[19]

Figure 3. (a) Schematic diagram of nanowires grown by VLS method; (b) TEM image of Ge nanowire grown by VLS method^[104]; (c) TEM image of Ge nanowires with diameter of (5 ± 0.6) nm prepared by laser ablation method and VLS method^[47]; (d) TEM image of Ge/Si core/shell nanowire with black Ge core and light gray Si shell^[105]; (e) high resolution TEM image of Ge/Si core/shell nanowire showing a crystalline Si shell^[105]; (f) schematic diagram of cross-section image and energy band offset of Ge/Si core/shell nanowire^[19].

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图 4 (a) Si衬底上沉积4.4个Ge原子层后的表面AFM图; (b) Si衬底上沉积Ge层以及退火之后形成的Ge量子线的表面AFM图^[41]; (c)和(d)分别是单根Ge量子线的扫描隧道显微镜图^[116] 以及横截面TEM图^[41]; (e) Si衬底上L形Ge量子线结构

Figure 4. (a) AFM image of Ge wetting layer after the growth of 4.4 monolayer Ge on Si substrate; (b) AFM image of Ge hut wire on Si substrate after the growth of Ge layer with subsequently annealing^[41]; (c), (d) scanning tunneling microscope image^[116] and cross-sectional TEM image of a Ge hut wire^[41]; (e) L-shaped Ge hut wires on Si substrate.

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图 5 (a)具有凹槽结构的Si (001)图形衬底的表面AFM图^[42]; (b)生长Si_0.75Ge_0.25层后形成一维SiGe条带结构的表面AFM图^[42]; (c) SiGe条带上形成Ge量子线的表面AFM图, 插图为量子线的晶面分析图, Ge量子线的两个侧面均为{105}晶面^[42]; (d)和(e)分别为Ge量子线的横截面STEM图及放大的STEM图^[42], 插图为Ge量子线的横截面全貌图; (f)和(g)分别为Ge量子线沿线方向的高分辨STEM图以及放大的STEM图^[42]; (h) Ge量子线各个生长阶段的AFM线扫描图^[42]

Figure 5. (a) AFM image of trench-patterned Si (001) substrate^[42]; (b) AFM image of SiGe mound after the growth of Si_0.75Ge_0.25 layer^[42]; (c) AFM image of Ge hut wire on Si_0.75Ge_0.25 mound after the Ge layer deposition with subsequently annealing, where inset image shows the {105} side faceted Ge hut wires^[42]; (d), (e) cross-sectional STEM image and magnified STEM image of a Ge hut wire, respectively^[42], where inset is the overall view of a hut wire; (f), (g) STEM image and magnified STEM image along a Ge hut wire, respectively^[42]; (h) AFM line-scans showing the growth process of a Ge hut wire^[42].

DownLoad: Full-Size Img PowerPoint

图 6 (a)—(d)在Si (001)衬底上凹槽边缘生长的紧邻平行排列的Ge量子线、长度为10 μm的Ge量子线、口字形和L形Ge量子线的AFM图^[42]; (e)—(g) Si (001)衬底上凹槽内部生长的Ge_0.33Si_0.67量子线的表面AFM图, 周期分别为1 μm, 2 μm及500 nm^[125]; (h)凹槽内部生长的单根Ge_0.33Si_0.67量子线的线扫描图, GeSi量子线的侧壁倾角为11.3°, 侧壁为{105}晶面^[125]

Figure 6. (a)−(d) AFM images of closely spaced parallel Ge hut wires, Ge hut wires with length of 10 μm, square-shaped and L-shaped Ge hut wires at the edges of trenches on Si (001) substrate, respectively^[42]; (e)−(g) AFM images of Ge_0.33Si_0.67 hut wires inside the trenches on Si (001) substrate with a period of 1 μm, 2 μm and 500 nm, respectively^[125]; (h) AFM line-scan of a Ge_0.33Si_0.67 hut wire inside the trench, which shows the {105} side facet with an inclination angle of 11.3°^[125].

DownLoad: Full-Size Img PowerPoint

图 7 (a)紧邻平行排列的Ge量子线AFM图; (b)双量子点器件结构示意图^[42]; (c)总电流I₁ + I₂与V_G1以及V_G2的变化关系图^[42]

Figure 7. (a) AFM image of the closely spaced parallel Ge hut wires; (b) schematic diagram of double quantum dot devices^[42]; (c) total current I₁ + I₂ versus V_G1 and V_G2^[42].

DownLoad: Full-Size Img PowerPoint

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Vol. 70, Issue 21 - 2021-11-05

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