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Stochastic collocation method for interconnect delay estimation in the presence of process variations

Li Xin Wang Janet M. Tang Wei-Qing

Stochastic collocation method for interconnect delay estimation in the presence of process variations

Li Xin, Wang Janet M., Tang Wei-Qing
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Publishing process
  • Received Date:  19 June 2008
  • Accepted Date:  22 October 2008
  • Published Online:  05 March 2009

Stochastic collocation method for interconnect delay estimation in the presence of process variations

  • 1. (1)南京理工大学计算机科学与技术学院,南京 210094; (2)亚利桑那大学电子工程系,美国亚利桑那州 AZ8742; (3)中国科学院计算技术研究所,北京 100190

Abstract: We present a process variations based stochastic collocation method to estimate interconnect delay. This method translates the strongly correlated process variations into orthogonal random variables by Cholesky decomposition. Polynomial chaos expression (PCE) and stochastic collocation method (SCM) are used to analyse the system response. A finite representation of interconnect delay is then obtained by using the collocation approach of minimizing the Hilbert space norm of the residual error. Experiment demonstrates that results obtained from the analysis method agree well with that from HSPICE simulation. The difference between the delays obtained from the analytical method and that from HSPICE is about 0.2% or less. Moreover, the method shows good computational efficiency, and much less running time has been observed compared with HSPICE simulation.

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