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Radiation effect and degradation mechanism in 65 nm CMOS transistor

Ma Wu-Ying Yao Zhi-Bin He Bao-Ping Wang Zu-Jun Liu Min-Bo Liu Jing Sheng Jiang-Kun Dong Guan-Tao Xue Yuan-Yuan

Radiation effect and degradation mechanism in 65 nm CMOS transistor

Ma Wu-Ying, Yao Zhi-Bin, He Bao-Ping, Wang Zu-Jun, Liu Min-Bo, Liu Jing, Sheng Jiang-Kun, Dong Guan-Tao, Xue Yuan-Yuan
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  • Received Date:  28 November 2017
  • Accepted Date:  07 February 2018
  • Published Online:  20 July 2019

Radiation effect and degradation mechanism in 65 nm CMOS transistor

    Corresponding author: Yao Zhi-Bin, yaozhibin@nint.ac.cn
  • 1. State Key Laboratory of Intense Pulsed Radiation Simulation and Effect, Xi'an 710024, China;
  • 2. Northwest Institute of Nuclear Technology, Xi'an 710024, China
Fund Project:  Project supported by the Major Program of the National Natural Science Foundation of China (Grant No. 11690043) and the State Key Laboratory of Intense Pulsed Radiation Simulation and Effect, China (Grant No. SKLIPR1505Z).

Abstract: Radiation effect of deep submicron semiconductor device has been extensively studied in recent years. However, fewer researches laid emphasis on the degradation characterization induced by total ionizing dose (TID) damage in nano-device. The purpose of this paper is to analyze the TID effect on the 65 nm commercial complementary metal oxide semiconductor transistor. The n-type and p-type metal oxide semiconductor field effect transistors (NMOSFET and PMOSFET) with different sizes are irradiated by 60Co γ rays at 50 rad (Si)/s, and TID is about 1 Mrad (Si). Static drain-current ID versus gate-voltage VG electrical characteristics are measured with semiconductor parameter measurement equipment. The irradiation bias of NMOSFET is as follows:the ON state is under gate voltage VG=+1.32 V, drain voltage VD is equal to source voltage VS (VD=VS=0), and the OFF state is under drain voltage VD=+1.32 V, gate voltage VG is equal to source voltage VS (VG=VS=0). The irradiation bias of PMOSFET is follows:the ON state is under gate voltage VG=0 V, drain voltage VD is equal to source voltage VS (VD=VS=1.32 V), and the OFF state is under VD=VG=VS=+1.32 V. The experimental results show that the negative shifts in the threshold voltage are observed in PMOSFET after irradiation. Besides, for PMOSFET the degradation of the ON state during radiation is more severe than that of the OFF state, whereas comparatively small effect are present in NMOSFET. Through experimental data and theoretical analysis, we find that the changes in the characteristics of the irradiated devices are attributed to the building up of positive oxide charges in the light doped drain (LDD) spacer oxide, rather than shallow trench isolation oxide degradation. The positive charges induced by TID in PMOSFET LDD spacer oxide will lead to the change of hole concentration in channel, which causes the threshold voltage to shift. What is more, the difference in electric field in the LDD spacer is the main reason for the difference in the radiation response between the two radiation bias conditions. Radiation-enabled technology computer aided design used to establish two-dimensional mode of the transistor. The simulation results of ID-VG curves are in good agreement with the experimental results. Combining theoretical analysis and numerical simulation, the radiation sensitive regions and the damage physical mechanism and radiation sensitivity regions of PMOSFETs are given. This work provides the helpful theory guidance and technical supports for the radiation hardening of the nano-devices used in the radiation environments.

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