Search

Article

x

留言板

尊敬的读者、作者、审稿人, 关于本刊的投稿、审稿、编辑和出版的任何问题, 您可以本页添加留言。我们将尽快给您答复。谢谢您的支持!

姓名
邮箱
手机号码
标题
留言内容
验证码

Electro-static discharge failure analysis and design optimization of gate-driver on array circuit in InGaZnO thin film transistor backplane

Ma Qun-Gang Zhou Liu-Fei Yu Yue Ma Guo-Yong Zhang Sheng-Dong

Electro-static discharge failure analysis and design optimization of gate-driver on array circuit in InGaZnO thin film transistor backplane

Ma Qun-Gang, Zhou Liu-Fei, Yu Yue, Ma Guo-Yong, Zhang Sheng-Dong
PDF
HTML
Get Citation
  • There is a risk of InGaZnO thin film transistor (IGZO TFT) failure, especially electro-static discharge (ESD) damage of gate driver on array (GOA) circuits, due to the combination of Cu interconnect, InGaZnO (IGZO) active layer and SiNx/SiO2 insulating layer used to realize large-scale ultra-high resolution display. It is found that the IGZO TFT damage position caused by ESD occurs between the source/drain metal layer and the gate insulator. The Cu metal of gate electrode diffuses into the gate insulator of SiNx/SiO2. The closer to the ESD damage area the IGZO TFT is, the more serious the negative bias of its threshold voltage (Vth) is until the device is fully turned on. The IGZO TFT with a large channel width-to-length ratio(W/L) in GOA circuit results in a serious negative bias of threshold voltage. In this paper, the ESD failure problem of GOA circuit in the IGZO TFT backplane is systematically analyzed by combining the ESD device level analysis with the system level analysis, which combines IGZO TFT device technology, difference in metal density between GOA region and active area on backplane, non-uniform thickness distribution of gate metal layer and gate insulator and so on. In the analysis of ESD device level, we propose that the diffusion of Cu metal from gate electrode into SiNx/SiO2 leads to the decrease of effective gate insulator layer, and that the built-in space charge effect leads to the decrease of the anti-ESD damage ability of IGZO TFT. In the analysis of ESD system level, we propose that the density of metal layers in GOA region is 4.5 times higher than that in active area of display panel, which makes the flatness of metal layer in GOA region worse. The non-uniformity of thickness of Cu metal film, SiNx film and SiO2 film around glass substrate lead to the position dependence of the anti-ESD damage ability of IGZO TFT in the GOA region. If there is a transition zone of film thickness change in IGZO TFT with large area, the ESD failure will occur easily. Accordingly, we propose to split large area IGZO TFT into several sub-TFT structures, which can effectively improve the ESD failure.
      Corresponding author: Zhang Sheng-Dong, zhangsd@pku.edu.cn
    [1]

    Marko S, Geert H, Chen S H, Kris M, Dimitri L 2018 Electrical Overstress/electrostatic Discharge Symposium Reno, September 23-28, 2018 p1

    [2]

    Liu Y, Chen R, Li B, En Y F, Chen Y Q 2017 IEEE Trans. Electron Dev. 1-5 99

    [3]

    Tai Y H, Chiu H L, Chou L S 2013 J. Disp. Technol. 9 613

    [4]

    Scholz M, Steudel S, Myny K, Chen S, Boschke R, Hellings G, Linten D 2016 Electrical Overstress/electrostatic Discharge Symposium Garden Grove, September 11-16, 2016 pp1-7.

    [5]

    宁洪龙, 胡诗犇, 朱峰, 姚日晖, 徐苗, 邹建华, 陶洪, 徐瑞霞, 徐华, 王磊, 兰林锋, 彭俊彪 2015 物理学报 64 126103

    Ning H L, Hu S B, Zhu F, Yao R H, Xu M, Zou J H, Tao H, Xu R X, Xu H, Wang L, Lan L F, Peng J B 2015 Acta Phys. Sin. 64 126103

    [6]

    Kim L Y, Kwon O K 2018 IEEE Electr. Device Lett. 39 43

    [7]

    Lin C L, Wu C E, Chen F H, Lai P C, Cheng M H 2016 IEEE Trans. Electron Dev. 63 2405

    [8]

    Geng D, Chen Y F, Mativenga M, Jin J 2015 IEEE Electr. Device Lett. 36 805

    [9]

    Chen W, Barnaby H J, Kozicki M N 2016 IEEE Electr. Device Lett. 37 580

    [10]

    Choi Z S, Mönig R, Thompson C V 2007 J. Appl. Phys. 102 387

    [11]

    Lee K W, Wang H, Bea J C, Murugesan M 2014 IEEE Electr. Device Lett. 35 114

    [12]

    Xiang L, Wang L L, Ning C, Hu H, Wei Y, Wang K, Yoo S Y, Zhang S D 2014 IEEE Trans. Electron Dev. 61 4299

    [13]

    Han K L, Ok K C, Cho H S, Oh S, Park J S 2017 Appl. Phys. Lett. 111 063502

    [14]

    Tari A, Lee C H, Wong W S 2015 Appl. Phys. Lett. 107 1679

    [15]

    Hung S C, Chiang C H, Li Y M 2015 J. Display Tech. 11 640

    [16]

    Hu C K, Gignac L M, Lian G 2018 IEEE International Electron Devices Meeting (IEDM) San Francisco, December 1-5, 2018

    [17]

    Thermadam S P, Bhagat S K, Alford T L, Sakaguchi Y, Kozicki M N, Mitkova M 2010 Thin Solid Films 518 3293

    [18]

    Toumi S, Ouennoughi Z, Strenger K C 2016 Solid State Electron. 122 56

    [19]

    Christen T 2017 IEEE T. Dielect. E. I. 23 3712

    [20]

    Choi S, Jang J, Kang H, Baeck J H, Bae J U, Park K S, Yoon S Y, Kang I B, Kim D M, Choi S J, Kim Y S, Oh S, Kim D H 2017 IEEE Electr. Device Lett. 38 580

    [21]

    Jang J, Kim D G, Kim D M, Choi S J, Kim D H 2014 Appl. Phys. Lett. 105 1117

    [22]

    强蕾, 姚若河 2012 物理学报 61 087303

    Qiang L, Yao R H 2012 Acta Phys. Sin. 61 087303

    [23]

    邓小庆, 邓联文, 何伊妮, 廖聪维, 黄生祥, 罗衡 2019 物理学报 68 057302

    Deng X Q, Deng L W, He Y N, Liao C W, Huang S X, Luo H 2019 Acta Phys. Sin. 68 057302

    [24]

    Wang W, Xu G W, Chowdhury M D H, Wang H, Um J K, Ji Z Y, Gao N, Zong Z W, Bi C, Lu C Y, Lu N D, Banerjee W, Feng J F, Li L, Kadashchuk A, Jang J, Liu M 2018 Phys. Rev. B 98 245

  • 图 1  13T1C架构的GOA电路单元原理图

    Figure 1.  Diagram of the GOA circuit unit composed of 13 TFTs and 1 capacitor.

    图 2  GOA电路的ESD破坏现象 (a) GOA区大面积的ESD烧伤现象; (b) M2 TFT的ESD破坏现象

    Figure 2.  ESD damage phenomenon of GOA circuit: (a) Photo image of the overall GOA where ESD damage occurs. (b) photo image of ESD damage M2 TFT in the GOA unit.

    图 3  M2 TFT的ESD失效区域解析 (a) ESD失效位置的FIB断面解析; (b) ESD失效位置的栅极绝缘层元素分析

    Figure 3.  Analysis of ESD failure area of M2 TFT: (a) FIB section analysis of ESD failure position; (b) elemental analysis of gate insulator at failure position of ESD.

    图 4  距离ESD失效中心不同位置的M2 TFT特性

    Figure 4.  M2 TFT characteristics at different positions from ESD failure center.

    图 5  Cu扩散引起的空间电荷效应与ESD失效机理

    Figure 5.  Mechanism of space charge effect formed by Cu2+ ion entering SiO2.

    图 6  Cu:SiNx/SiO2三层薄膜的厚度等值线分布

    Figure 6.  Thickness contour distribution of Cu: SiNx/SiO2 three films.

    表 1  GOA区M2 TFT不同设计方案比较

    Table 1.  Comparison of different design schemes of M2 TFT in GOA.

    结构 2个子TFT 6个子TFT 8个子TFT
    版图
    版图空间 274.5 μm × 259.2 μm 274.5 μm × 300.2 μm 274.5 μm × 351.2 μm
    扫描线面积 53158.8 59647.3 65519.6
    数据线面积 43155.8 46190.2 49248.2
    扫描线密度 74.71% 72.4% 68%
    数据线密度 60.7% 56.1% 51.1%
    DownLoad: CSV
  • [1]

    Marko S, Geert H, Chen S H, Kris M, Dimitri L 2018 Electrical Overstress/electrostatic Discharge Symposium Reno, September 23-28, 2018 p1

    [2]

    Liu Y, Chen R, Li B, En Y F, Chen Y Q 2017 IEEE Trans. Electron Dev. 1-5 99

    [3]

    Tai Y H, Chiu H L, Chou L S 2013 J. Disp. Technol. 9 613

    [4]

    Scholz M, Steudel S, Myny K, Chen S, Boschke R, Hellings G, Linten D 2016 Electrical Overstress/electrostatic Discharge Symposium Garden Grove, September 11-16, 2016 pp1-7.

    [5]

    宁洪龙, 胡诗犇, 朱峰, 姚日晖, 徐苗, 邹建华, 陶洪, 徐瑞霞, 徐华, 王磊, 兰林锋, 彭俊彪 2015 物理学报 64 126103

    Ning H L, Hu S B, Zhu F, Yao R H, Xu M, Zou J H, Tao H, Xu R X, Xu H, Wang L, Lan L F, Peng J B 2015 Acta Phys. Sin. 64 126103

    [6]

    Kim L Y, Kwon O K 2018 IEEE Electr. Device Lett. 39 43

    [7]

    Lin C L, Wu C E, Chen F H, Lai P C, Cheng M H 2016 IEEE Trans. Electron Dev. 63 2405

    [8]

    Geng D, Chen Y F, Mativenga M, Jin J 2015 IEEE Electr. Device Lett. 36 805

    [9]

    Chen W, Barnaby H J, Kozicki M N 2016 IEEE Electr. Device Lett. 37 580

    [10]

    Choi Z S, Mönig R, Thompson C V 2007 J. Appl. Phys. 102 387

    [11]

    Lee K W, Wang H, Bea J C, Murugesan M 2014 IEEE Electr. Device Lett. 35 114

    [12]

    Xiang L, Wang L L, Ning C, Hu H, Wei Y, Wang K, Yoo S Y, Zhang S D 2014 IEEE Trans. Electron Dev. 61 4299

    [13]

    Han K L, Ok K C, Cho H S, Oh S, Park J S 2017 Appl. Phys. Lett. 111 063502

    [14]

    Tari A, Lee C H, Wong W S 2015 Appl. Phys. Lett. 107 1679

    [15]

    Hung S C, Chiang C H, Li Y M 2015 J. Display Tech. 11 640

    [16]

    Hu C K, Gignac L M, Lian G 2018 IEEE International Electron Devices Meeting (IEDM) San Francisco, December 1-5, 2018

    [17]

    Thermadam S P, Bhagat S K, Alford T L, Sakaguchi Y, Kozicki M N, Mitkova M 2010 Thin Solid Films 518 3293

    [18]

    Toumi S, Ouennoughi Z, Strenger K C 2016 Solid State Electron. 122 56

    [19]

    Christen T 2017 IEEE T. Dielect. E. I. 23 3712

    [20]

    Choi S, Jang J, Kang H, Baeck J H, Bae J U, Park K S, Yoon S Y, Kang I B, Kim D M, Choi S J, Kim Y S, Oh S, Kim D H 2017 IEEE Electr. Device Lett. 38 580

    [21]

    Jang J, Kim D G, Kim D M, Choi S J, Kim D H 2014 Appl. Phys. Lett. 105 1117

    [22]

    强蕾, 姚若河 2012 物理学报 61 087303

    Qiang L, Yao R H 2012 Acta Phys. Sin. 61 087303

    [23]

    邓小庆, 邓联文, 何伊妮, 廖聪维, 黄生祥, 罗衡 2019 物理学报 68 057302

    Deng X Q, Deng L W, He Y N, Liao C W, Huang S X, Luo H 2019 Acta Phys. Sin. 68 057302

    [24]

    Wang W, Xu G W, Chowdhury M D H, Wang H, Um J K, Ji Z Y, Gao N, Zong Z W, Bi C, Lu C Y, Lu N D, Banerjee W, Feng J F, Li L, Kadashchuk A, Jang J, Liu M 2018 Phys. Rev. B 98 245

  • [1] Ma Qun-Gang, Wang Hai-Hong, Zhang Sheng-Dong, Chen Xu, Wang Ting-Ting. Electro-static discharge protection analysis and design optimization of interlayer Cu interconnection in InGaZnO thin film transistor backplane. Acta Physica Sinica, 2019, 68(15): 158501. doi: 10.7498/aps.68.20190646
    [2] Chai Chang-Chun, Li Yue-Jin, Liu Jing, Wang Jia-You, Yang Yin-Tang, Wu Zhen-Yu. The temperature characteristics of stress-induced voiding in Cu interconnects. Acta Physica Sinica, 2009, 58(4): 2625-2630. doi: 10.7498/aps.58.2625
    [3] Deng Xiao-Qing, Deng Lian-Wen, He Yi-Ni, Liao Cong-Wei, Huang Sheng-Xiang, Luo Heng. Leakage current model of InGaZnO thin film transistor. Acta Physica Sinica, 2019, 68(5): 057302. doi: 10.7498/aps.68.20182088
    [4] Zhang Li-Rong, Ma Xue-Xue, Wang Chun-Fu, Li Guan-Ming, Xia Xing-Heng, Luo Dong-Xiang, Wu Wei-Jing, Xu Miao, Wang Lei, Peng Jun-Biao. High speed gate driver circuit basd on metal oxide thin film transistors. Acta Physica Sinica, 2016, 65(2): 028501. doi: 10.7498/aps.65.028501
    [5] Zou Jian-Hua, Lan Lin-Feng, Xu Rui-Xia, Yang Wei, Peng Jun-Biao. Integration of organic thin-film transistor and polymer light-emitting diodes. Acta Physica Sinica, 2010, 59(2): 1275-1281. doi: 10.7498/aps.59.1275
    [6] Qin Ting, Huang Sheng-Xiang, Liao Cong-Wei, Yu Tian-Bao, Deng Lian-Wen. Analytical channel potential model of amorphous InGaZnO thin-film transistors with synchronized symmetric dual-gate. Acta Physica Sinica, 2017, 66(9): 097101. doi: 10.7498/aps.66.097101
    [7] Yuan Guang-Cai, Xu Zheng, Zhao Su-Ling, Zhang Fu-Jun, Sun Qin-Jun, Xu Xu-Rong, Xu Na. Study of the characteristics of organic thin film transistors with phenyltrimethoxysilane buffer under low gate modulation voltage. Acta Physica Sinica, 2009, 58(7): 4941-4947. doi: 10.7498/aps.58.4941
    [8] Zhang Shi-Yu, Yu Zhi-Nong, Cheng Jin, Wu De-Long, Li Xu-Yang, Xue Wei. Effects of annealing temperature and Ga content on properties of solution-processed InGaZnO thin film. Acta Physica Sinica, 2016, 65(12): 128502. doi: 10.7498/aps.65.128502
    [9] Xu Piao-Rong, Qiang Lei, Yao Ruo-He. A technique for extracting the density of states of the linear region in an amorphous InGaZnO thin film transistor. Acta Physica Sinica, 2015, 64(13): 137101. doi: 10.7498/aps.64.137101
    [10] Liu Yu-Rong, Chen Wei, Liao Rong. Low-operating-voltage polymer thin-film transistors based on poly(3-hexylthiophene). Acta Physica Sinica, 2010, 59(11): 8088-8092. doi: 10.7498/aps.59.8088
    [11] Wang Xiong, Cai Xi-Kun, Yuan Zi-Jian, Zhu Xia-Ming, Qiu Dong-Jiang, Wu Hui-Zhen. Study of zinc tin oxide thin-film transistor. Acta Physica Sinica, 2011, 60(3): 037305. doi: 10.7498/aps.60.037305
    [12] Nie Guo-Zheng, Zou Dai-Feng, Zhong Chun-Liang, Xu Ying. Analysis of improved characteristics of pentacene thin-film transistor with an embedded copper oxide layer. Acta Physica Sinica, 2015, 64(22): 228502. doi: 10.7498/aps.64.228502
    [13] Wang Yuan, Zhang Li-Zhong, Cao Jian, Lu Guang-Yi, Jia Song, Zhang Xing. Research on electrostatic discharge characteristics of tunnel field effect transistors. Acta Physica Sinica, 2014, 63(17): 178501. doi: 10.7498/aps.63.178501
    [14] Zhang Fang, Li Juan, Wu Chun-Ya, Zhao Shu-Yun, Liu Jian-Ping, Meng Zhi-Guo, Xiong Shao-Zhen. Investigation on stability of microcrystalline silicon thin film transistors. Acta Physica Sinica, 2006, 55(12): 6612-6616. doi: 10.7498/aps.55.6612
    [15] Liu Yu-Rong, Wang Zhi-Xin, Yu Jia-Le, Xu Hai-Hong. High mobility polymer thin-film transistors. Acta Physica Sinica, 2009, 58(12): 8566-8570. doi: 10.7498/aps.58.8566
    [16] Sun Qin-Jun, Xu Zheng, Zhao Su-Ling, Zhang Fu-Jun, Gao Li-Yan, Tian Xue-Yan, Wang Yong-Sheng. Contact effect in organic thin film transistors. Acta Physica Sinica, 2010, 59(11): 8125-8130. doi: 10.7498/aps.59.8125
    [17] Wu Hui-Zhen, Zhang Ying-Ying, Wang Xiong, Zhu Xia-Ming, Yuan Zi-Jian, Xu Tian-Ning. Fabrication and performance of indium oxide based transparent thin film transistors. Acta Physica Sinica, 2010, 59(7): 5018-5022. doi: 10.7498/aps.59.5018
    [18] Qiang Lei, Yao Ruo-He. Distributions of the threshold voltage and the temperature in the channel of amorphous silicon thin film transistors. Acta Physica Sinica, 2012, 61(8): 087303. doi: 10.7498/aps.61.087303
    [19] Zhao Kong-Sheng, Xuan Rui-Jie, Han Xiao, Zhang Geng-Ming. Junctionless low-voltage thin-film transistors based on indium-tin-oxide. Acta Physica Sinica, 2012, 61(19): 197201. doi: 10.7498/aps.61.197201
    [20] Chen Xiao-Xue, Yao Ruo-He. DC characteristic research based on surface potential for a-Si:H thin-film transistor. Acta Physica Sinica, 2012, 61(23): 237104. doi: 10.7498/aps.61.237104
  • Citation:
Metrics
  • Abstract views:  780
  • PDF Downloads:  14
  • Cited By: 0
Publishing process
  • Received Date:  27 February 2019
  • Accepted Date:  11 March 2019
  • Available Online:  01 May 2019
  • Published Online:  20 May 2019

Electro-static discharge failure analysis and design optimization of gate-driver on array circuit in InGaZnO thin film transistor backplane

    Corresponding author: Zhang Sheng-Dong, zhangsd@pku.edu.cn
  • 1. School of Electronic and Computer Engineering, Peking University, Shenzhen 518055, China
  • 2. School of Electronics Engineering and Computer Science, Peking University, Beijing 100871, China
  • 3. Nanjing CEC Panda FPD Technology Co., Ltd., Nanjing 210033, China

Abstract: There is a risk of InGaZnO thin film transistor (IGZO TFT) failure, especially electro-static discharge (ESD) damage of gate driver on array (GOA) circuits, due to the combination of Cu interconnect, InGaZnO (IGZO) active layer and SiNx/SiO2 insulating layer used to realize large-scale ultra-high resolution display. It is found that the IGZO TFT damage position caused by ESD occurs between the source/drain metal layer and the gate insulator. The Cu metal of gate electrode diffuses into the gate insulator of SiNx/SiO2. The closer to the ESD damage area the IGZO TFT is, the more serious the negative bias of its threshold voltage (Vth) is until the device is fully turned on. The IGZO TFT with a large channel width-to-length ratio(W/L) in GOA circuit results in a serious negative bias of threshold voltage. In this paper, the ESD failure problem of GOA circuit in the IGZO TFT backplane is systematically analyzed by combining the ESD device level analysis with the system level analysis, which combines IGZO TFT device technology, difference in metal density between GOA region and active area on backplane, non-uniform thickness distribution of gate metal layer and gate insulator and so on. In the analysis of ESD device level, we propose that the diffusion of Cu metal from gate electrode into SiNx/SiO2 leads to the decrease of effective gate insulator layer, and that the built-in space charge effect leads to the decrease of the anti-ESD damage ability of IGZO TFT. In the analysis of ESD system level, we propose that the density of metal layers in GOA region is 4.5 times higher than that in active area of display panel, which makes the flatness of metal layer in GOA region worse. The non-uniformity of thickness of Cu metal film, SiNx film and SiO2 film around glass substrate lead to the position dependence of the anti-ESD damage ability of IGZO TFT in the GOA region. If there is a transition zone of film thickness change in IGZO TFT with large area, the ESD failure will occur easily. Accordingly, we propose to split large area IGZO TFT into several sub-TFT structures, which can effectively improve the ESD failure.

    • InGaZnO薄膜晶体管(InGaZnO thin-film transistor, IGZO TFT)已成为大尺寸超高分辨率显示的主流驱动技术, 但其背板发生静电释放(electro-static discharge, ESD)的失效风险较高. 目前的研究主要是针对单个IGZO TFT器件进行传输线脉冲(transmission line pulse, TLP)或者人体静电放电模式(human body model, HBM)测试分析, 找出ESD影响因素并提出ESD鲁棒性高的器件结构与保护结构. Marko等[1]从IGZO TFT的器件结构上对ESD进行了研究. Liu等[2] 用TLP测试方法研究发现, TFT的沟道击穿仅取决于ESD应力电压水平, 而应力电压水平与栅极绝缘层有关. Tai等[3]发现, 导致IGZO TFT静电击穿的ESD功率主要受源漏极接触电阻的影响, 而不受IGZO有源层质量的影响. Scholz等[4]提出, IGZO有源层的低迁移率导致ESD的鲁棒性仅为0.3 mA/μm, 优化ESD保护设计是关键. Ning等[5]和Kim等[6]提出, 源漏极采用Cu-Mo或者Mo-Ti/Cu叠层结构的IGZO TFT具有较高的迁移率和更低的接触电阻, 有利于提高IGZO TFT的可靠性.

      大尺寸超高分辨率面板为了实现无边框设计, 需要在显示区周边集成阵列基板栅极驱动(gate driver on array, GOA)电路[7,8]. 显示区的IGZO TFT尺寸都采用同样的宽长比(W/L), 而GOA电路的每个单元都密集分布着十多个不同W/L的IGZO TFT. 这样的GOA单元在扫描线两侧同时设计, UHD和QUHD面板上的数量分别达到4320个和8640个. 另外, GOA电路位于基板玻璃或者面板的周边, ESD风险相对更高. 通过调整GOA电路单元的器件组合、扫描线ESD保护电路结构、TFT开关态电压大小等参数, 发现ESD破坏的改善效果并不明显. 所以, 有必要在分析IGZO TFT器件的ESD应力的基础上, 对玻璃基板上的IGZO TFT, 特别是GOA电路中的IGZO TFT, 进行系统级的ESD研究, 并通过规模生产进行对策验证.

      综合IGZO TFT器件工艺、GOA区与显示区金属密度比、栅极金属层与绝缘层厚度非均匀性分布等因素, 采用系统级ESD分析方法, 提出栅极Cu:SiNx/SiO2界面缺陷是导致GOA电路中IGZO TFT发生ESD失效的基本要素, GOA电路区域金属密度比高以及Cu:SiNx/SiO2三层薄膜厚度分布的非均匀性是诱发ESD失效的重要因素. Cu原子晶界扩散和界面扩散的激活能分别只有1.2 eV和0.7—1.0 eV, 小于Al的扩散激活能1.48 eV[9,10]. Cu会扩散进入SiNx/SiO2[11]. 因此, 栅极Cu:SiNx/SiO2界面性质关系到IGZO TFT可靠性. GOA区与显示区的Cu金属密度相差悬殊, 在工艺上容易引起GOA区的Cu:SiNx/SiO2界面缺陷[12-14]. 对应地, 我们提出了降低GOA电路中大尺寸IGZO TFT发生ESD失效风险的设计结构.

    2.   GOA电路和ESD实验分析
    • 本研究的IGZO TFT背板的各层薄膜自玻璃基板起依次是Mo/Cu栅极层、SiNx/SiO2栅极绝缘层、IGZO有源层、Mo/Cu源漏极层、SiO2/SiNx保护层. 扫描线左右两侧的GOA驱动电路采用由13个IGZO TFT和1个电容构成的13T1C架构(图1). 该架构在4T1C架构基础上增加了GOA电路信赖性提升单元和辅助帧电荷清除单元, 其输入信号有: 初始置位信号GSP、时钟信号CLK1-CLK8、清空信号CLR和关态低电位VSS. 采用8根CLK可以降低时钟信号线的负载, 满足对上升时间的要求, 在降低功耗的同时提升显示区像素的充电能力[15]. 设计55寸UHD面板像素时, 保证数据线信号和扫描线脉冲信号的交叠时间控制在2 μs以内, 输出使能(output enable, OE)时间为1.8 μs, 以防止错误的数据线信号充入像素.

      Figure 1.  Diagram of the GOA circuit unit composed of 13 TFTs and 1 capacitor.

      在13个IGZO TFT中, M2的沟道W/L最大, 达到2400 μm/8 μm. M2 TFT是扫描线脉冲信号的上拉模块, 其沟道宽度W越大, 扫描线脉冲信号的上升时间和下降时间越小. 上升时间越小, 预留的充电时间越长, 像素电压的充电率越高; 下降时间越小, 充入像素的信号电压越准确. M2 TFT沟道宽度的设计需要综合考虑版图空间.

    • 在IGZO TFT背板制作以及面板没有绑定IC前, 容易发生如图2(a)所示的GOA区域大面积ESD烧伤现象. 其中, 8根CLK的总线区①、GOA电路区②、扫描线ESD保护区③的合计总宽度约为5 mm. ESD烧伤区域从破坏严重的中心GOA单元向上下GOA单元传播, 范围可达到4 mm×10 mm. GOA电路右侧的扫描线ESD保护电路和左侧的时钟信号线受到ESD破坏的影响较小. 出现这种烧伤问题的GOA电路, 集中在玻璃基板边缘, 玻璃基板中央基本没有.

      Figure 2.  ESD damage phenomenon of GOA circuit: (a) Photo image of the overall GOA where ESD damage occurs. (b) photo image of ESD damage M2 TFT in the GOA unit.

      对驱动IC绑定前的所有工序加强ESD保护对策后, GOA区域的大面积ESD烧伤现象有效减少. 但是, 依然存在个别IGZO TFT的ESD失效现象, 其中M2 TFT的ESD失效现象最严重. 如图2(b)所示, 观察到的ESD突发性损伤位置呈黑点状或者黑块状分布. 同时可以推断, 其他位置的IGZO TFT可能存在ESD潜在性损伤. 所以, 要系统研究IGZO TFT背板GOA电路的ESD失效机理.

    • GOA电路的M2 TFT在扫描线ESD保护单元工作之前发生ESD破坏, 说明M2 TFT的抗ESD能力低. 在发生ESD破坏的M2 TFT中, 选取如图2(b)所示的A, B两个黑点状和黑块状位置, 利用FIB解析ESD破坏位置的各膜层状态, 发现ESD破坏发生在栅极绝缘层成膜后、源漏极金属层成膜前(图3(a)).

      Figure 3.  Analysis of ESD failure area of M2 TFT: (a) FIB section analysis of ESD failure position; (b) elemental analysis of gate insulator at failure position of ESD.

      I-V特性正常的M2 TFT栅极绝缘层进行EDS分析, 发现栅极Cu金属层上方的SiNx/SiO2绝缘层中, 在靠近SiO2的SiNx层中存在Cu原子成分(图3(b)). 初步判断, 栅极Cu原子扩散到SiNx/SiO2绝缘层中, 是影响IGZO TFT器件性能与导致ESD失效的一个重要因素.

      为了建立IGZO TFT器件性能恶化与ESD失效之间的关系, 针对沟道W/L最大、ESD破坏最严重的M2 TFT, 从靠近ESD烧伤区到远离ESD烧伤区, 分别检测器件的I-V特性. 如图4所示, 样品发生ESD烧伤的中心位置在第100个GOA单元到第200个GOA单元之间, 远离ESD烧伤区的M2 TFT(M2-450)特性正常, 越靠近ESD烧伤区的M2 TFT阈值电压(Vth)负漂越严重, 电流开关比越小, 直到器件(M2-100和M2-150)的源漏极与栅极完全短路.

      Figure 4.  M2 TFT characteristics at different positions from ESD failure center.

      作为对比, 我们检测了靠近烧伤区的M1 TFT, M4 TFT, M7 TFT和M12 TFT等其他器件, I-V特性正常. 这表明沟道W/L最大的M2 TFT发生ESD破坏的风险最高; 并且, M2 TFT阈值电压负漂的绝对值与ESD破坏风险具有正相关性, 部分阈值电压负漂严重的M2 TFT已经导致对应的总线处于漏电状态.

    3.   ESD失效机理分析
    • 栅极Cu金属在Cu:SiNx/SiO2界面的粘附性直接影响到Cu在SiNx/SiO2绝缘层中的扩散速率[16]. 用PECVD沉积SiNx/SiO2薄膜时, 等离子体不断地对Cu表面物理轰击并在Cu表面反应依次形成SiNx/SiO2. 由于SiNx/SiO2成膜时薄膜内的晶粒之间存在空隙, 部分Cu原子沿着SiNx/SiO2中的空隙扩散, 并在原来位置形成空隙, 在SiNx/SiO2中形成类似晶须的结构, 成为深能级杂质, 使器件性能退化甚至失效[17]. 栅极Cu与栅极绝缘层SiNx/SiO2界面的Cu表面的hillocks凸起位置, 是Cu离子向SiNx/SiO2层扩散的拥挤点. 一旦在栅极和源漏极(ESD stress ①), 或者栅极和IGZO有源层(ESD stress②)之间形成一定的压降, Cu与SiNx/SiO2界面由于电极反应产生大量的Cu离子, 向SiNx/SiO2层扩散, 在SiNx/SiO2层形成陷阱态. 如图5所示, Cu离子向IGZO沟道方向移动并大量积累, 形成空间电荷效应, 使IGZO层与SiNx/SiO2栅极绝缘层的表面势垒厚度减少, 势垒降低. Cu离子带正电, 扩散到SiNx/SiO2层形成空间分布状态, 会改变栅极绝缘层内电场强度的空间分布. 可以用泊松方程描述Cu离子扩散形成空间电荷效应的机理[18,19]:

      Figure 5.  Mechanism of space charge effect formed by Cu2+ ion entering SiO2.

      其中, U是SiNx/SiO2电势, F是电场强度, q是Cu离子所带电荷, C是Cu离子浓度, ε0是真空介电常数, εr是相对介电常数.

      IGZO TFT阈值电压Vth负漂, 可以看成是多种机制的组合, 即ΔVth, tot = Vth1 + Vth2 + ··· [20-22]. 图4中靠近ESD烧伤中心区的IGZO TFT阈值电压负漂的关键影响因素是栅极Cu扩散进入栅极绝缘层SiNx/SiO2引起的有效栅极绝缘层厚度减小以及内建电场效应. 由于内建电场效应, 当栅极和源漏极(ESD stress ①)或者栅极和IGZO有源层(ESD stress②)之间存在电压分布, 随着IGZO能带弯曲, IGZO有源层中的电子就很容易越过降低后的势垒, 在栅极绝缘层的陷阱态中进行跳跃导电, 甚至注入形成场致发射. 如果场致发射电流Igen接近限制电流, SiNx/SiO2栅极绝缘层的阻抗RGI将从高阻态变为低阻态, 丧失绝缘性能, 导致TFT器件失效[23]. Qiang等[22]和Wang等[24]提出, 用IGZO TFT栅极电压产生的强垂直电场的效应有助于捕获的载流子直接隧穿进入导电带, 并导致几乎与温度无关的迁移率.

    • Cu金属薄膜在PVD沉积过程中会形成晶界缺陷. 在后续的等离子体高温工艺中, 随着应力释放再结晶, Cu表面会产生hillocks. 玻璃基板边缘的GOA电路中, M2 TFT栅极Cu表面的hillocks凸起最为严重, 栅极Cu: SiNx/SiO2界面的Cu离子最容易向SiNx/SiO2层扩散, 导致GOA区M2 TFT容易出现ESD失效.

      影响玻璃基板周边M2 TFT栅极Cu表面的hillocks凸起, 主要有两个因素, 包括GOA区与显示区金属层密度比差异大导致的周边金属层平坦度低, 以及玻璃基板周边Cu金属膜厚和SiNx/SiO2膜厚的均匀性差导致的栅极Cu:SiNx/SiO2性质稳定性低.

      以3840×2160分辨率的 55寸IGZO TFT背板为例, GOA区域对应栅极金属层和源漏极金属层的Cu金属覆盖密度分别达到54%和68%, 是显示区(active area, AA)的4.42倍和4.48倍. GOA区与AA区的Cu金属覆盖密度差值太大, GOA区的Cu金属层平坦性较差, 导致Cu表面hillocks凸起更严重.

      图6所示, 玻璃基板周边的GOA电路(GOA-1和GOA-2)中, Cu金属、SiNx薄膜、SiO2薄膜的厚度起伏明显, 均匀性较差. 而玻璃基板中央的GOA电路(GOA-3)中, 三层薄膜厚度均匀性较好. 所以, 位于玻璃基板边缘的GOA电路中, Cu表面的hillocks凸起较严重, 栅极绝缘层的耐压差异较大, ESD失效风险较高.

      Figure 6.  Thickness contour distribution of Cu: SiNx/SiO2 three films.

    4.   结果与讨论
    • 根据前面的ESD破坏区域解析和ESD失效机理分析, 得到栅极Cu: SiNx/SiO2界面缺陷引起的ESD失效机理: 面板周边GOA电路, 特别是其中的M2 TFT, 栅极Cu金属层的面积最大, 厚度起伏最明显, hillocks凸起等缺陷最严重, 扩散到SiNx/SiO2层的Cu离子最多. 同时, 位于玻璃基板周边的GOA区的SiNx/SiO2薄膜相对较薄, 随着栅极的Cu离子扩散进入SiNx/SiO2层, 原本较薄的栅极绝缘层的有效厚度进一步减小, 导致栅极和源漏极之间的漏电流急剧增大到限制电流的临界电压, 此电压比玻璃基板中央区域的要小. 在IGZO层或者源漏极金属层与栅极Cu金属层之间积累到一定电荷的压降后, 栅极与IGZO层或者源漏极金属层之间瞬间形成电流通道, 导致器件失效, 甚至大面积烧伤.

      根据以上的ESD失效机理, 为了提高GOA电路ESD鲁棒性, 工艺上可以提高IGZO TFT背板的Cu金属表面平坦性、Cu: SiNx/SiO2界面结合的紧密性、栅极绝缘层SiNx/SiO2的厚度均匀性, 设计上可以分解大面积的栅极Cu金属块.

      表1所示, 把原来一分为二的M2 TFT, 分解为6个子TFT并联和8个子TFT并联的结构. 一方面, 降低了栅极和源漏极的金属层密度, 降低同一个TFT内栅极Cu金属层和SiNx/SiO2栅极绝缘层厚度的起伏程度; 另一方面, 提高了M2 TFT失效区域的可切割修复能力.

      结构 2个子TFT 6个子TFT 8个子TFT
      版图
      版图空间 274.5 μm × 259.2 μm 274.5 μm × 300.2 μm 274.5 μm × 351.2 μm
      扫描线面积 53158.8 59647.3 65519.6
      数据线面积 43155.8 46190.2 49248.2
      扫描线密度 74.71% 72.4% 68%
      数据线密度 60.7% 56.1% 51.1%

      Table 1.  Comparison of different design schemes of M2 TFT in GOA.

    5.   结 论
    • 栅极Cu:SiNx/SiO2和有源层IGZO是实现大尺寸超高分辨率显示的基本组合. 该组合的一个风险是IGZO TFT器件易失效, 特别是GOA电路中大尺寸IGZO TFT容易发生ESD失效. 本文针对GOA电路中IGZO TFT的ESD失效发生区域, 分析了器件膜层结构的变化、栅极Cu离子在栅极绝缘层SiNx/SiO2中的扩散, 以及ESD传播路径上的IGZO TFT特性变化. 在ESD器件级分析中, 提出了栅极Cu金属在栅极绝缘层SiNx/SiO2中的扩散导致有效栅极绝缘层减小, 以及内建空间电荷效应导致IGZO TFT抗ESD应力能力的减弱. 在ESD系统级分析中, 提出GOA区与显示区金属层的密度比差异导致GOA区金属层平坦度较差, 玻璃基板周边Cu金属薄膜、SiNx薄膜和SiO2薄膜的厚度非均匀性大导致GOA区的IGZO TFT抗ESD应力能力存在位置依存性, 如果尺寸大的IGZO TFT覆盖膜厚变化过渡区, 容易引起ESD失效. 相应地, 我们提出把大尺寸IGZO TFT拆分成多个子TFT的设计结构, 可以有效改善ESD失效现象.

Reference (24)

Catalog

    /

    返回文章
    返回