具有L型源极场板的双槽绝缘体上硅高压器件新结构

石艳梅; 刘继芝; 姚素英; 丁燕红; 张卫华; 代红丽

doi:10.7498/aps.63.237305

留言板

尊敬的读者、作者、审稿人, 关于本刊的投稿、审稿、编辑和出版的任何问题, 您可以本页添加留言。我们将尽快给您答复。谢谢您的支持!

姓名

邮箱

手机号码

标题

留言内容

验证码

摘要

为了提高小尺寸绝缘体上硅(SOI)器件的击穿电压, 同时降低器件比导通电阻, 提出了一种具有L型源极场板的双槽SOI高压器件新结构. 该结构具有如下特征: 首先, 采用了槽栅结构, 使电流纵向传导面积加宽, 降低了器件的比导通电阻; 其次, 在漂移区引入了SiO2槽型介质层, 该介质层的高电场使器件的击穿电压显著提高; 第三, 在槽型介质层中引入了L型源极场板, 该场板调制了漂移区电场, 使优化漂移区掺杂浓度大幅增加, 降低了器件的比导通电阻. 二维数值仿真结果表明: 与传统SOI结构相比, 在相同器件尺寸时, 新结构的击穿电压提高了151%, 比导通电阻降低了20%; 在相同击穿电压时, 比导通电阻降低了80%. 与相同器件尺寸的双槽SOI结构相比, 新结构保持了双槽SOI结构的高击穿电压特性, 同时, 比导通电阻降低了26%.

关键词:

作者及机构信息

1.
天津大学电子信息工程学院, 天津 300072;

2.
天津理工大学电子信息工程学院, 天津 300384;

3.
电子科技大学微电子与固体电子学院, 成都 610054

基金项目: 国家自然科学基金(批准号:51101113)和天津市自然科学基金(批准号:13JCQNJC,14JCYBJC16200)资助的课题.

参考文献

[1]	Luo X R, Zhang B, Li Z J 2008 IEEE Trans. Electron Dev. 55 1756
[2]	Wu L J, Hu S D, Zhang B, Li Z J 2011 Chin. Phys. B 20 027101
[3]	Zhou K, Luo X R, Fan Y H, Luo Y C, Hu X R, Zhang B 2013 Chin. Phys. B 22 067306
[4]	Hu C 1979 IEEE Trans. Electron Dev. 26 243
[5]	Zhang B, Wang W L, Chen W J, Li Z H, Li Z J 2009 IEEE Electron Dev. Lett. 30 849
[6]	Yang F J, Gong J, Su R Y, Huo K H, Tsai C L, Cheng C C, Liou R H, Tuan H C, Huang C F 2013 IEEE Trans. Electron Dev. 60 2847
[7]	Son W S, Sohn Y H, Choi S Y 2003 Electron. Lett. 39 1760
[8]	Zhang W T, Qiao M, Wu L J, Ye K, Wang Z, Wang Z G, Luo X R, Zhang S, Su W, Zhang B, Li Z J 2013 Proceedings of the 25th International Symposium on Power Semiconductor Devices & ICs Kanazawa, Japan, May 26-30 2013 p329
[9]	Fan J, Zhang B, Luo X R, Li Z J 2013 Chin. Phys. B 22 118502
[10]	Wang Z G, Zhang B, Fu Q, Xie G, Li Z J 2012 IEEE Electron Dev. Lett. 33 703
[11]	Kim S L, Yang H Y, Choi Y I 2000 Proceedings of the 22nd International Conference on Microelectronics Nis, Serbia, May 14-17, 2000 p641
[12]	Luo X R, Luo Y C, Fan Y, Hu G Y, Wang X W, Zhang Z Y, Fan Y H, Cai J Y, Wang P, Zhou K 2013 Chin. Phys. B 22 027304
[13]	Shi Y M, Liu J Z, Yao S Y, Ding Y H 2014 Acta Phys. Sin. 63 107302 (in Chinese) [石艳梅, 刘继芝, 姚素英, 丁燕红 2014 物理学报 63 107302]
[14]	Ge R, Luo X R, Jiang Y H, Zhou K, Wang P, Wang Q, Wang Y G, Zhang B, Li Z J 2012 J. Semicond. 33 074005
[15]	Fujishima N, Sugi A, Kajiwara S, Matsubara K, Nagayasu Y, Salama C A T 2002 IEEE Trans. Electron Dev. 49 1462
[16]	Luo X R, Fan J, Wang Y G, Lei T F, Qiao M, Zhang B, Udrea F 2011 IEEE Electron Dev. Lett. 32 185
[17]	Luo X R, Lei T F, Wang Y G, Yao G L, Jiang Y H, Zhou K, Wang P, Zhang Z Y 2012 IEEE Trans. Electron Dev. 59 504
[18]	Hu X R, Zhang B, Luo X R, Jiang Y H, Li Z J 2012 Electron. Lett. 48 1235
[19]	Luo X R, Yao G L, Zhang Z Y, Jiang Y H, Zhou K, Wang P, Wang Y G 2012 Chin. Phys. B 21 068501

施引文献

[1]	Luo X R, Zhang B, Li Z J 2008 IEEE Trans. Electron Dev. 55 1756
[2]	Wu L J, Hu S D, Zhang B, Li Z J 2011 Chin. Phys. B 20 027101
[3]	Zhou K, Luo X R, Fan Y H, Luo Y C, Hu X R, Zhang B 2013 Chin. Phys. B 22 067306
[4]	Hu C 1979 IEEE Trans. Electron Dev. 26 243
[5]	Zhang B, Wang W L, Chen W J, Li Z H, Li Z J 2009 IEEE Electron Dev. Lett. 30 849
[6]	Yang F J, Gong J, Su R Y, Huo K H, Tsai C L, Cheng C C, Liou R H, Tuan H C, Huang C F 2013 IEEE Trans. Electron Dev. 60 2847
[7]	Son W S, Sohn Y H, Choi S Y 2003 Electron. Lett. 39 1760
[8]	Zhang W T, Qiao M, Wu L J, Ye K, Wang Z, Wang Z G, Luo X R, Zhang S, Su W, Zhang B, Li Z J 2013 Proceedings of the 25th International Symposium on Power Semiconductor Devices & ICs Kanazawa, Japan, May 26-30 2013 p329
[9]	Fan J, Zhang B, Luo X R, Li Z J 2013 Chin. Phys. B 22 118502
[10]	Wang Z G, Zhang B, Fu Q, Xie G, Li Z J 2012 IEEE Electron Dev. Lett. 33 703
[11]	Kim S L, Yang H Y, Choi Y I 2000 Proceedings of the 22nd International Conference on Microelectronics Nis, Serbia, May 14-17, 2000 p641
[12]	Luo X R, Luo Y C, Fan Y, Hu G Y, Wang X W, Zhang Z Y, Fan Y H, Cai J Y, Wang P, Zhou K 2013 Chin. Phys. B 22 027304
[13]	Shi Y M, Liu J Z, Yao S Y, Ding Y H 2014 Acta Phys. Sin. 63 107302 (in Chinese) [石艳梅, 刘继芝, 姚素英, 丁燕红 2014 物理学报 63 107302]
[14]	Ge R, Luo X R, Jiang Y H, Zhou K, Wang P, Wang Q, Wang Y G, Zhang B, Li Z J 2012 J. Semicond. 33 074005
[15]	Fujishima N, Sugi A, Kajiwara S, Matsubara K, Nagayasu Y, Salama C A T 2002 IEEE Trans. Electron Dev. 49 1462
[16]	Luo X R, Fan J, Wang Y G, Lei T F, Qiao M, Zhang B, Udrea F 2011 IEEE Electron Dev. Lett. 32 185
[17]	Luo X R, Lei T F, Wang Y G, Yao G L, Jiang Y H, Zhou K, Wang P, Zhang Z Y 2012 IEEE Trans. Electron Dev. 59 504
[18]	Hu X R, Zhang B, Luo X R, Jiang Y H, Li Z J 2012 Electron. Lett. 48 1235
[19]	Luo X R, Yao G L, Zhang Z Y, Jiang Y H, Zhou K, Wang P, Wang Y G 2012 Chin. Phys. B 21 068501

引用本文:

Citation:

计量

文章访问数: 1104
PDF下载量: 407
被引次数: 0

具有L型源极场板的双槽绝缘体上硅高压器件新结构

1. 天津大学电子信息工程学院, 天津 300072;

2. 天津理工大学电子信息工程学院, 天津 300384;

3. 电子科技大学微电子与固体电子学院, 成都 610054

基金项目:

国家自然科学基金(批准号:51101113)和天津市自然科学基金(批准号:13JCQNJC,14JCYBJC16200)资助的课题.

收稿日期: 2014-06-30

修回日期: 2014-07-28

刊出日期: 2014-12-05

摘要: 为了提高小尺寸绝缘体上硅(SOI)器件的击穿电压, 同时降低器件比导通电阻, 提出了一种具有L型源极场板的双槽SOI高压器件新结构. 该结构具有如下特征: 首先, 采用了槽栅结构, 使电流纵向传导面积加宽, 降低了器件的比导通电阻; 其次, 在漂移区引入了SiO2槽型介质层, 该介质层的高电场使器件的击穿电压显著提高; 第三, 在槽型介质层中引入了L型源极场板, 该场板调制了漂移区电场, 使优化漂移区掺杂浓度大幅增加, 降低了器件的比导通电阻. 二维数值仿真结果表明: 与传统SOI结构相比, 在相同器件尺寸时, 新结构的击穿电压提高了151%, 比导通电阻降低了20%; 在相同击穿电压时, 比导通电阻降低了80%. 与相同器件尺寸的双槽SOI结构相比, 新结构保持了双槽SOI结构的高击穿电压特性, 同时, 比导通电阻降低了26%.

关键词:

A dual-trench silicon on insulator high voltage device with an L-shaped source field plate

1.
School of Electronics Information Engineering, Tianjin University, Tianjin 300072, China;

2.
School of Electronics Information Engineering, Tianjin University of Technology, Tianjin 300384, China;

3.
School of Microelectronics and Solid-State Electronics, University of Electronic Science and Technology of China, Chengdu 610054, China

Fund Project:

Project supported by the National Natural Science Foundation of China (Grant No. 51101113) and the Natural Science Foundation of Tianjin, China (Grant Nos. 13JCQNJC, 14JCYBJC16200).

Received Date: 30 June 2014

Accepted Date: 28 July 2014

Published Online: 05 December 2014

Abstract: To improve the breakdown voltage and reduce the specific on-resistance of a small size silicon on insulator (SOI) device, a dual-trench SOI high voltage device with an L-shaped source field plate is proposed. The device has the features as follows: first, a trench gate is adopted. The trench gate widens the current conduction area and makes the current conduction path shorter, thus lowering the specific on-resistance. Second, a SiO2 dielectric layer is introduced into the drift region. This dielectric layer can hold a high electric field, which makes the breakdown voltage greatly increased. Third, an L-shaped source field plate is introduced. This field plate modulates the electric field in the drift region, so increases the optimized doping concentration of the drift region significantly and reduces the specific on-resistance. The results from the two-dimensional semiconductor simulator show that as compared with a conventional SOI device at the same cell pitch, the breakdown voltage is increased by 151%, and the specific on-resistance is reduced by 20%. The specific on-resistance is reduced by 80% at the same breakdown voltage. Compared with a dual-trench SOI device with the same cell pitch, the proposed device maintains the same high breakdown voltage as the dual- trench SOI device, and at the same time, the specific on-resistance is decreased by 26%.

Keywords:

全文HTML

参考文献 (19)

搜索

留言板