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硅通孔(TSV)是三维集成电路的一种主流技术.基于TSV寄生参数提取模型,对不同物理尺寸的TSV电阻-电容(RC)参数进行提取,采用Q3D仿真结果验证了模型精度.分析TSVRC效应对片上系统的性能及功耗影响,推导了插入缓冲器的三维互连线延时与功耗的解析模型.在45nm互补金属氧化物半导体工艺下,对不同规模的互连电路进行了比较分析.模拟结果显示,TSVRC效应导致互连延时平均增加10%,互连功耗密度平均提高21%;电路规模越小,TSV影响愈加显著.在三维片上系统前端设计中,包含TSV寄生参数的互连模型将有助于设计者更加精确地预测片上互连性能.Through-silicon-via (TSV) is one of the major design techniques in three- dimensional integrated circuit (3D IC). Based on the parasitic parameter extraction model, the parasitic resistance-capacitance (RC) parameters for different size TSVs are acquired and validated with Q3D simulation data. Using the results of this model, closed-form delay and power consumption expressions for buffered interconnect used in 3D IC are presented. Comparative results with 3D net without TSV in various cases show that TSV RC effect has a huge influence on delay and power of 3D IC, which leads maximum delay and power comsumption to extra increase 10% and 21\% on average, respectively. It is crucial to correctly establish a TSV-aware 3D interconnect model in 3D IC front-end design.
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Keywords:
- 3D integrated circuit /
- TSV /
- interconnect delay /
- power consumption
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[34] Zhu Z M, Hao B T, Yang Y T, Li Y J 2010 Chin. Phys. B 19 127805
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[38] -
[1] Pavlidis V F, Friedman E G 2009 Three-Dimensional Integrated Circuit Design (San Mateo: Morgan Kaufmann) p15
[2] [3] Savidis I, Friedman E G 2009 IEEE Trans. Electron Dev. 56 1873
[4] [5] Katti G, Stucchi M, Meyer K D, Dehaene W 2010 IEEE Trans. Electron Dev. 57 256
[6] Kim D H, Mukhopadhyay S, Lim S K 2009 Proceeding of the 11th International Workshop on System Level Interconnect Prediction San Francisco, July 2627, 2009 p85
[7] [8] Amirali S Y, Xiang H, Yu W J, Popovich M 2009 Proceeding of the Conference on Design, Automation Test in Europe Belgium, March 1418, 2009 p288
[9] [10] Karmarkar A P, Xu X P, Moroz V 2009 IEEE 47th Annual Interna-tional Reliability Physics Symposium Montreal, April 1519, 2009 p682
[11] [12] Kim D H, Lim S K 2010 Proceeding of the 12th International Workshop on System Level Interconnect Prediction Anaheim, June 1314, 2010 p25
[13] [14] [15] Chen P Y, Wu C W, Kwai D M 2009 Proceeding of the 2009 Asian Test Symposium Taiwan, November 2326, 2009 p450
[16] Xu C, Li H, Suaya R, Banerjee K 2010 IEEE Trans. Electron Dev. 57 3405
[17] [18] Hall S H, Hall G W, McCall J A 2000 High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices (New York: John Wiley Sons) p205
[19] [20] Li X, Wang J M, Tang W Q 2009 Acta Phys. Sin. 58 3603 (in Chinese) [李鑫, Wang Janet M, 唐卫清 2009 物理学报 58 3603]
[21] [22] Banerjee K, Mehrotra A 2002 IEEE Trans. Electron Dev. 49 2001
[23] [24] Zhu Z M, Hao B T, Li R, Yang Y T 2010 Acta Phys. Sin. 59 1997 (in Chinese) [朱樟明, 郝报田, 李儒, 杨银堂 2009 物理学报 59 1997]
[25] [26] [27] Dong G, Xue Y, Li J W, Yang Y T 2011 Acta Phys. Sin. 60 46602 (in Chinese) [董刚, 薛荫, 李建伟, 杨银堂 2011 物理学报 60 046602]
[28] [29] Davis J A, De V K, Meindl J D 1998 IEEE Trans. Electron Dev. 45 580
[30] [31] Sekar D C, Naeemi A, Sarvari R, Davis J A, Meindl J D 2007 IEEE/ACM International Conference on Computer-Aided Design San Jose, November 48, 2007 p560
[32] [33] Zhu Z M, Zhong B, Hao B T, Yang Y T 2009 Acta Phys. Sin. 58 7124 (in Chinese) [朱樟明, 钟波, 郝报田, 杨银堂 2009 物理学报 58 7124]
[34] Zhu Z M, Hao B T, Yang Y T, Li Y J 2010 Chin. Phys. B 19 127805
[35] [36] [37] Davis J A, Meindl J D 2003 Interconnect Technology and Design for Gig Scale Integration (Netherlands: Springer) p184
[38]
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