Carbon based electronic technology in  post-Moore era: progress, applications and challenges

Liu Yi-Fan; Zhang Zhi-Yong

doi:10.7498/aps.71.20212076

Abstract

In the past 60 years, silicon-based semiconductor technology has triggered off the profound change of our information society, but it is also gradually approaching to the physical limit and engineering limit as well. Thus, the global semiconductor industry has entered into the post-Moore era. Carbon nanotube has many excellent electronic properties such as high mobility and ultra-thin body, so it has become a hopeful candidate for the new semiconductor material in the post-Moore era. After more than 20 years of development, carbon based electronic technology has made fundamental breakthroughs in many basic problems such as material preparation, Ohmic metal-semiconductor contact and gate engineering. In principle, there is no insurmountable obstacle in its industrialization process now. Therefore, in this paper the intrinsic advantages of carbon based electronic technology in the post-Moore era is introduced, the basic problems, progress and optimization direction of carbon based electronic technology are summarized, the application prospects in the fields of digital circuits, radio frequency electronics, sensing and detection, three-dimensional integration and chips for special applications are presented. Finally, the comprehensive challenges to the industrialization of carbon based electronic technology are analyzed, and its future development is also prospected.

Keywords:

Authors and contacts

Key Laboratory for the Physics and Chemistry of Nanodevices, Center for Carbon-based Electronics, Peking University, Beijing 100871, China

Corresponding author: Zhang Zhi-Yong, zyzhang@pku.edu.cn

Funds: Project supported by the National Key Research and Development Program (Grant No. 2016YFA0201901).

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图 1 碳纳米管及碳纳米管晶体管示意图　(a) (14, 7)半导体性碳纳米管截面图; (b) (14, 7)半导体性碳纳米管侧视图; (c) 首个P型自对准结构碳纳米管晶体管^[12]; (d) 首个N型自对准结构碳纳米管晶体管^[13]

Figure 1. Schematic diagram of carbon nanotube and carbon nanotube transistors: (a) Cross section of (14, 7) semiconducting carbon nanotube; (b) side view of (14, 7) semiconducting carbon nanotube; (c) the first P-type self-aligned carbon nanotube transistor^[12]; (d) the first N-type self-aligned carbon nanotube transistor^[13].

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图 2 (a) 理想的阵列碳纳米管顶栅晶体管示意图^[31]; (b) 不同制备方法得到的碳纳米管的密度和半导体纯度对比, 其中蓝色方框区域为理想指标区间^[31]

Figure 2. (a) Schematic diagram of an ideal carbon nanotube array top gate transistor^[31]; (b) comparison of the density and semiconductor purity of carbon nanotubes prepared by different methods, where the blue box area is the ideal index range^[31].

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图 3 多次提纯实现高纯半导体性碳纳米管溶液的流程^[31]

Figure 3. Process for obtaining high purity semiconducting carbon nanotube solution through multiple purifications^[31].

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图 4 DLSA法碳纳米管阵列自组装技术^[31]　(a) DLSA法自组装原理示意图; (b) 阵列碳纳米管晶体管的输出曲线; (c) 阵列碳纳米管晶体管的跨导对比; (d) 阵列碳纳米管环振电路的输出频谱

Figure 4. DLSA self-assembly technology for carbon nanotube array^[31]: (a) Principle schematic diagram of DLSA self-assembly; (b) output curves of a carbon nanotube array transistor; (c) benchmarking transconductance of carbon nanotube array transistors; (d) output frequency spectrum for a ring oscillator circuit made of carbon nanotube array.

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图 5 碳纳米管无掺杂CMOS技术^[63]　(a) 以金属Pd作为P型电极, 以金属Sc作为N型电极的碳纳米管CMOS示意图; (b) 碳纳米管CMOS的迁移率特性

Figure 5. Doping free carbon nanotube CMOS technology^[63]: (a) Schematic diagram of the carbon nanotube CMOS with metal Pd as P-type electrode and metal Sc as N-type electrode; (b) mobility characteristics of the carbon nanotube CMOS.

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图 6 碳纳米管晶体管的不同接触构型以及接触电阻的缩减规律　(a) 碳化钼末端接触示意图^[68]; (b) 碳化钼末端接触的接触电阻缩减规律(红色直线)^[68]; (c) 金属Pd或Sc作侧边接触的接触电阻缩减规律^[67]; (d) 金属电极侧边接触及电荷注入转移长度示意图^[67]

Figure 6. Different contact configurations of carbon nanotube transistors and the scaling trend of contact resistance: (a) Schematic diagram of molybdenum carbide end contact^[68]; (b) the contact resistance’s scaling trend of molybdenum carbide end contact (red straight line)^[68]; (c) the contact resistance’s scaling trend of metal Pd or Sc as side contacts^[67]; (d) schematic diagram of metal electrode side contact and transfer length of charge injection^[67].

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图 7 两种典型的碳纳米管栅介质　(a) 无定形碳辅助形核的ALD法氧化铪(约3.5 nm)^[19]; (b) 金属蒸镀后热氧化形成的氧化钇(约5 nm)^[91]

Figure 7. Two typical kinds of carbon nanotube gate dielectrics: (a) ALD hafnium oxide with amorphous carbon assisted nucleation (～3.5 nm) ^[19]; (b) yttrium oxide formed by thermal oxidation after metal evaporation (～5 nm) ^[91].

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图 8 栅介质缺陷导致的栅氧电荷效应　(a) 各种栅氧电荷示意图; (b) 随机固定电荷主导的阈值电压波动^[102]; (c) 碳纳米管MOS结构的界面态密度粗略估计^[99]

Figure 8. Gate oxide charge effects caused by various dielectric defects: (a) Schematic diagram of various gate oxide charges; (b) threshold voltage fluctuation dominated by random fixed charges^[102]; (c) a rough estimation of interface states density in a carbon nanotube MOS structure^[99].

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图 9 不同栅金属对碳纳米管晶体管阈值电压的调制　(a) 单一金属的分立功函数调制^[17]; (b) 叠层金属的准连续功函数调制, 底层是变厚度的钯, 顶层是固定厚度的钪^[104]

Figure 9. Threshold voltage modulation of carbon nanotube transistor using different gate metals: (a) Discrete work function modulation using single metal layer^[17]; (b) quasi continuous work function modulation using a metal stack, the bottom layer is palladium with variable thickness, and the top layer is scandium with fixed thickness^[104].

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图 10 三种双极性抑制技术　(a), (b), (c) 反馈栅结构示意图、能带图和转移曲线对比^[107]; (d), (e), (f) SCMOS示意图、能带图和转移曲线对比^[108]; (g), (h), (i) L型栅结构示意图、能带图和转移曲线对比^[106]

Figure 10. Three bipolar suppression techniques: (a), (b), (c) Schematic diagram, energy band diagram and transfer curve comparison of feedback gate structure^[107]; (d), (e), (f) schematic diagram, energy band diagram and transfer curve comparison of SCMOS structure^[108]; (g), (h), (i) schematic diagram, energy band diagram and transfer curve comparison of L-type gate structure^[106].

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图 11 碳纳米管晶体管的scaling down极限^[19]　(a), (c) P型和N型碳纳米管晶体管的透射电子显微镜(TEM)截面图, 其中沟道和栅极长度分别为20 nm和10 nm; (b), (d) 碳纳米管和硅CMOS FET的门延迟和能量延迟积(EDP)随栅长缩减的变化趋势比较, 蓝色实线表示P型硅FET的实验数据拟合, 而绿色实线表示N型硅FET, 蓝色星和绿色星分别代表P型和N型碳纳米管晶体管; (e), (f) 5 nm栅长碳纳米管晶体管的扫描电子显微镜(SEM)俯视图及其转移特性曲线

Figure 11. Scaling down limit of carbon nanotube transistors^[19]. (a), (c) Cross-sectional TEM micrographs of P-type and N-type carbon nanotube FETs, where the channel and gate lengths are respectively 20 nm and 10 nm. (b), (d) comparisons of scaling trends of gate delay and EDP between CNT and Si CMOS FETs. Blue solid line indicates the experiment data fitting for the P-type Si-MOSFETs, whereas green solid line indicates the N-type Si-MOSFETs, the blue and green stars respectively represent the P-type and N-type CNTFETs. (e), (f) SEM top view and transfer characteristic curves of a 5 nm gate length carbon nanotube transistor.

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图 12 基于碳纳米管沟道和石墨烯电极的狄拉克冷源晶体管(DSFET)^[30]　(a) DSFET的器件结构及能带示意图; (b) DSFET的亚60特性机理分析; (c) DSFET的转移特性曲线(红色); (d) 不同亚60器件的SS与I₆₀分布对比

Figure 12. Dirac cold source transistor based on carbon nanotube channel and graphene electrode^[30]: (a) Device structure and energy band diagram of DSFET; (b) mechanism analysis of sub-60 characteristic of DSFET; (c) transfer characteristic curve (red) of DSFET; (d) comparison of SS and I₆₀ distribution among different sub-60 devices.

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图 13 碳纳米管CMOS器件和电路的制备及数字逻辑功能演示　(a) 高度对称的碳纳米管CMOS输出特性曲线^[51]; (b) 碳纳米管4位全加器的照片^[51]; (c) 120个典型顶栅碳纳米管FET的输出特性曲线(V_ds = –1 V)^[50]; (d) 碳纳米管4位全加器的逻辑测试结果(V_DD = –2 V)^[51]

Figure 13. Fabrication of carbon nanotube CMOS devices and circuits, and demonstration of digital logic functions: (a) Output characteristic curves of highly symmetrical carbon nanotube CMOS^[51]; (b) micrograph depicting a carbon nanotube 4-bit full adder^[51]; (c) transfer characteristic curves of 120 typical top-gate carbon nanotube FETs, V_ds = –1 V^[50]; (d) functionality measurements of the carbon nanotube 4-bit full adder at a V_DD of –2 V ^[51].

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图 14 碳纳米管阵列射频晶体管的频率特性^[20], 其中(a) 器件沟道区域的SEM照片, (b) 器件本征截止频率随栅长缩减的变化规律, (c) 本征截止频率处于太赫兹应用范围内; 碳纳米管阵列射频放大器的功率增益和线性度特性^[20], 其中(d) 放大器测试电路的示意图, (e) 18 GHz工作频率下的输出增益特性, (f) 不同射频放大器的OIP3/P_d.c.特性对比

Figure 14. Frequency characteristics of carbon nanotube array RF transistors^[20]: (a) SEM photos of device’s channel region; (b) the scaling trend of intrinsic cut-off frequency under different gate lengths; (c) the intrinsic cut-off frequency is in the terahertz application range. Power gain and linearity of carbon nanotube array RF amplifiers^[20]: (d) Schematic diagram of the amplifier test circuit; (e) output gain characteristics at 18 GHz; (f) comparison of OIP3/P_d.c.characteristics of different RF amplifiers.

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图 15 基于碳纳米管浮栅晶体管的生物传感器^[148]与气体传感器^[22]　(a) 碳纳米管生物传感器示意图^[148]; (b) 碳纳米管生物传感器对DNA序列的检测限^[148]; (c) 碳纳米管生物传感器对囊泡的检测限^[148]; (d) 碳纳米管氢气传感器示意图^[22]; (e) 碳纳米管氢气传感器工作在100 ℃的检测限^[22]; (f) 碳纳米管氢气传感器的响应率和检测限分布, 浅蓝色椭圆区域为核电安全应用范围^[22]

Figure 15. Biosensor^[148] and gas sensor^[22] based on the carbon nanotube floating gate transistor: (a) Schematic diagram of the carbon nanotube biosensor^[148]; (b) the limit of detection (LOD) of a carbon nanotube biosensor for DNA sequence^[148]; (c) LOD of a carbon nanotube biosensor for vesicles^[148]; (d) schematic diagram of the carbon nanotube hydrogen sensor^[22]; (e) LOD of a carbon nanotube hydrogen sensor operating under 100 ℃^[22]; (f) the response rate and LOD distribution of carbon nanotube hydrogen sensor, and the light blue oval area is the scope of nuclear power safety application^[22].

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图 16 感存算传一体化的高能效碳基三维集成电路示意图^[154]

Figure 16. Schematic diagram of high energy efficiency 3D integrated circuit based on the carbon nanotube, which integrates sensing, memory, computing and transmission components^[154].

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图 17 抗辐照可修复的碳纳米管晶体管与电路^[23]　(a) Co-60 γ射线对器件的辐射损伤示意图; (b) 聚酰亚胺衬底上印刷的离子胶碳纳米管晶体管的照片; (c) 离子胶类CMOS反相器的多次辐照损伤和修复过程; (d) 离子胶抗辐照碳纳米管晶体管和反相器的性能对比

Figure 17. Radiation-hardened and repairable carbon nanotube transistors and circuits^[23]: (a) Schematic diagram of radiation damage to devices by Co-60 γ-ray; (b) photograph of printed ion gel CNT FETs on polyimide substrates; (c) multiple cycles of irradiation and repairing of ion gel CMOS-like inverters; (d) performance benchmark of radiation-hardened ion gel CNT FETs and inverters.

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表 1 300 nm栅长下不同器件结构的碳纳米管场效应晶体管参数比较^[106]

Table 1. Benchmark of CNT FETs with different device structures at the same gate length of 300 nm^[106].

Structure	I_off /(nA·μm^–1)	SS/(mV·dec^–1)	On/off ratio	Self-aligned process	Scalability
FBG	0.49	73	3.84 × 10⁶	No	No
Normal-spacer	15.85	85	8.91 × 10⁴	Yes	Yes
HD BOX	5.75	80	6.17 × 10⁵	No	No
L-shaped-spacer	0.38	70	1.73 × 10⁶	Yes	Yes

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表 2 碳基电子技术产业化进程中的综合性挑战

Table 2. Comprehensive challenges in the industrialization of carbon based electronic technology

挑战类别	发展目标
挑战类别	近期	中长期	长期
材料	各指标满足研发需求、制备8 in晶圆	各指标满足碳基超大规模集成电路需求	洁净度达到业界标准、制备12 in大晶圆
器件工艺	接触电阻优化、栅结构和漏端工程	碳基平面集成工艺、硅基后道工艺兼容	碳基三维集成工艺、硅基前道工艺兼容
均一性和可靠性	优化材料均一性和器件工艺可靠性	开发碳基器件和电路的钝化封装工艺	提高超大规模碳基集成电路的良率
电路与系统设计	器件模型及PDK	完整EDA工具	三维集成系统、TPU等新型架构
标准化平台	材料制备表征平台、器件电路测试平台	工艺研发平台、工艺制造平台	碳基芯片生产平台

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