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With the development of hardware-optimized deployment of piking neural networks (SNNs), SNN processors based on field-programmable gate arrays (FPGAs) have become a research hotspot due to their efficiency and flexibility. However, existing methods rely on multi-timestep training and reconfigurable computing architectures, which increases computational and memory overhead, thus reducing deployment efficiency. This work presents an efficient and lightweight residual SNN accelerator that combines algorithm and hardware co-design to optimize inference energy efficiency. In terms of algorithm, we employ single-timesteps training, integrate grouped convolutions, and fuse batch normalization (BN) layers, thus compressing the network to only 0.69 M parameters. Quantization-aware training (QAT) further constrains all weights and activations to 8-bit precision. In terms of hardware, the reuse of intra-layer resource maximizes FPGA utilization, a full pipeline cross-layer architecture improves throughput, and on-chip block RAM (BRAM) stores network parameters and intermediate results to improve memory efficiency. The experimental results show that the proposed processor achieves a classification accuracy of 87.11% on the CIFAR-10 dataset, with an inference time of 3.98 ms per image and an energy efficiency of 183.5 FPS/W. Compared with mainstream graphics processing unit (GPU) platforms, it achieves more than double the energy efficiency. Furthermore, compared with other SNN processors, it achieves at least a fourfold increase in inference speed and a fivefold improvement in energy efficiency.
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图 1 ResNet-10脉冲神经网络结构
Figure 1. ResNet-10 spiking neural network structure.
图 2 标准卷积与分组卷积下ResNet-10各层参数量对比
Figure 2. Comparison of parameter counts for each layer of ResNet-10 under standard convolution and group convolution.
图 3 不同条件下测试准确率对比
Figure 3. Comparison of test accuracy under different conditions.
图 4 残差SNN处理器硬件总体架构图
Figure 4. Overall hardware architecture of the residual SNN processor.
图 5 卷积操作示意图
Figure 5. Schematic diagram of the convolution operation.
图 6 流水线设计 (a) 卷积数据处理流水线结构; (b)层间全流水架构
Figure 6. Pipeline design: (a) Convolution data processing pipeline structure; (b) fully pipelined inter-layer architecture.
表 1 残差SNN处理器资源利用率
Table 1. Resource utilization of residual SNN processors.
名称 消耗资源 可用资源 百分比/% LUTs 134859 425280 31.71 FF 341722 850560 40.18 BRAM 674.5 1080 62.45 DSP 3008 4272 70.41 
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表 2 处理器和GPU平台在CIFAR-10数据集上的性能表现
Table 2. Performance of the processor and GPU platform on the CIFAR-10 dataset.
硬件平台 ZCU216 FPGA GeForce RTX 4060 Ti 准确率/% 88.11 88.33 功耗/W 1.369 51 单张图片推理
时间/ms3.98 0.243 FPS 251 4115 FPS/W 183.5 80.7
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表 3 在CIFAR-10数据集上与其他SNN处理器的性能比较
Table 3. Performance comparison with other SNN processors on the CIFAR-10 dataset.
平台 E3NE[21] SCPU[22] SiBrain[23] Aliyev et al.[24] 本文> FPGA型号 XCVU13 P Virtex-7 Virtex-7 XCVU13 P ZCU216 频率/MHz 150 200 200 100 100 SNN模型 AlexNet ResNet-11 CONVNet(VGG-11) VGG-9 ResNet-10 模型深度 8 11 6(11) 9 10 精度/bits 6 8 8(8) 4 8 参数量/M — — 0.3(9.2) — 0.69 LUTs/FFs 48k/50k 178k/127k 167k/136k(140k/122k) — 135k/342k 准确率/% 80.6 90.60 82.93(90.25) 86.6 87.11 功率/W 4.7 1.738 1.628(1.555) 0.73 1.369 时延/ms 70 25.4 1.4(18.9) 59 3.98 FPS 14.3 39.43 696(53) 16.95 251 FPS/W 3.0 22.65 438.8(34.1) 23.21 183.5
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