具有纵向漏极场板的低导通电阻绝缘体上硅横向双扩散金属氧化物半导体器件新结构

石艳梅; 刘继芝; 姚素英; 丁燕红

doi:10.7498/aps.63.107302

留言板

尊敬的读者、作者、审稿人, 关于本刊的投稿、审稿、编辑和出版的任何问题, 您可以本页添加留言。我们将尽快给您答复。谢谢您的支持!

姓名

邮箱

手机号码

标题

留言内容

验证码

摘要

为降低绝缘体上硅（SOI）横向双扩散金属氧化物半导体（LDMOS）器件的导通电阻，同时提高器件击穿电压，提出了一种具有纵向漏极场板的低导通电阻槽栅槽漏SOI-LDMOS器件新结构. 该结构特征为采用了槽栅槽漏结构，在纵向上扩展了电流传导区域，在横向上缩短了电流传导路径，降低了器件导通电阻；漏端采用了纵向漏极场板，该场板对漏端下方的电场进行了调制，从而减弱了漏极末端的高电场，提高了器件的击穿电压. 利用二维数值仿真软件MEDICI对新结构与具有相同器件尺寸的传统SOI结构、槽栅SOI结构、槽栅槽漏SOI 结构进行了比较. 结果表明：在保证各自最高优值的条件下，与这三种结构相比，新结构的比导通电阻分别降低了53%，23%和提高了87%，击穿电压则分别提高了4%、降低了9%、提高了45%. 比较四种结构的优值，具有纵向漏极场板的槽栅槽漏SOI结构优值最高，这表明在四种结构中新结构保持了较低导通电阻，同时又具有较高的击穿电压.

关键词:

槽栅 /
槽漏 /
低导通电阻 /
击穿电压

作者及机构信息

1.
天津大学电子信息工程学院, 天津 300072;

2.
天津理工大学电子信息工程学院, 天津 300384;

3.
电子科技大学微电子与固体电子学院, 成都 610054

基金项目: 国家自然科学基金（批准号：51101113）资助的课题.

参考文献

[1]	Tan Y, Cai J, Sin Johnny K O 2001 IEEE Trans. Electron Dev. 48 2428
[2]	Bi J S, Hai C H, Han Z S 2011 Acta Phys. Sin. 60 018501 (in Chinese) [毕津顺, 海潮和, 韩郑生 2011 60 018501]
[3]	Wang Y G, Luo X R, Ge R, Wu L J, Chen X, Yao G L, Lei T F, Wang Q, Fan J, Hu X R 2011 Chin. Phys. B 20 077304
[4]	Luo X R, Zhang B, Li Z J, Guo Y F, Tang X W, Liu Y 2007 IEEE Electron Dev. Lett. 28 422
[5]	Li Q, Zhang B, Li Z J 2008 Acta Phys. Sin. 57 6565 (in Chinese) [李琦, 张波, 李肇基 2008 物理学报 57 6565]
[6]	Wu L J, Hu S D, Zhang B, Luo X R, Li Z J 2011 Chin. Phys. B 20 087101
[7]	Wu L J, Zhang W T, Zhang B, Li Z J 2013 J. Semicond. 34 044008
[8]	Hu C 1979 IEEE Trans. Electron Dev. 26 243
[9]	Kawaguchi Y, Sano T, Nakagawa A 1999 IEEE International Electron Devices Meeting Washington DC, USA, December 5-8, 1999 p197
[10]	Erlbacher T, Bauer A J, Frey L 2010 IEEE Electron Dev. Lett. 31 464
[11]	Luo X R, Yao G L, Zhang Z Y, Jiang Y H, Zhou K, Wang P, Wang Y G, Lei T F, Zhang Y X, Wei J 2012 Chin. Phys. B 21 068501
[12]	Yue L, Zhang B, Li Z J 2012 IEEE Electron Dev. Lett. 33 1174
[13]	Luo X R, Lei T F, Wang Y G, Yao G L, Jiang Y H, Zhou K, Wang P, Zhang Z Y 2012 IEEE Trans. Electron Dev. 59 504
[14]	Luo X R, Fan J, Wang Y G, Lei T F, Qiao M, Zhang B, Udrea F 2011 IEEE Electron Dev. Lett. 32 185
[15]	Baba Y, Yanagiya S, Koshino Y, Udo Y 1994 Proceedings of the 6th International Power Semiconductor Devices and ICs Davos, Switzerland, May 31-June 2, 1994 p183
[16]	Kim S L, Yang H Y, Choi Y I 2000 Proceedings of the 22nd International Conference on Microelectronics Nis, Serbia, May 14-17, 2000 p641
[17]	Ge R, Luo X R, Jiang Y H, Zhou K, Wang P, Wang Q, Wang Y G, Zhang B, Li Z J 2012 J. Semicond. 33 074005
[18]	Zhang H P, Jiang L F, Sun L L, Li W J, Zhou L, Hua B X, Xu L Y, Lin M 2007 International Symposium on Communications and Information Technologies Sydney, Australia, October 17-19, 2007 p34

施引文献

[1]	Tan Y, Cai J, Sin Johnny K O 2001 IEEE Trans. Electron Dev. 48 2428
[2]	Bi J S, Hai C H, Han Z S 2011 Acta Phys. Sin. 60 018501 (in Chinese) [毕津顺, 海潮和, 韩郑生 2011 60 018501]
[3]	Wang Y G, Luo X R, Ge R, Wu L J, Chen X, Yao G L, Lei T F, Wang Q, Fan J, Hu X R 2011 Chin. Phys. B 20 077304
[4]	Luo X R, Zhang B, Li Z J, Guo Y F, Tang X W, Liu Y 2007 IEEE Electron Dev. Lett. 28 422
[5]	Li Q, Zhang B, Li Z J 2008 Acta Phys. Sin. 57 6565 (in Chinese) [李琦, 张波, 李肇基 2008 物理学报 57 6565]
[6]	Wu L J, Hu S D, Zhang B, Luo X R, Li Z J 2011 Chin. Phys. B 20 087101
[7]	Wu L J, Zhang W T, Zhang B, Li Z J 2013 J. Semicond. 34 044008
[8]	Hu C 1979 IEEE Trans. Electron Dev. 26 243
[9]	Kawaguchi Y, Sano T, Nakagawa A 1999 IEEE International Electron Devices Meeting Washington DC, USA, December 5-8, 1999 p197
[10]	Erlbacher T, Bauer A J, Frey L 2010 IEEE Electron Dev. Lett. 31 464
[11]	Luo X R, Yao G L, Zhang Z Y, Jiang Y H, Zhou K, Wang P, Wang Y G, Lei T F, Zhang Y X, Wei J 2012 Chin. Phys. B 21 068501
[12]	Yue L, Zhang B, Li Z J 2012 IEEE Electron Dev. Lett. 33 1174
[13]	Luo X R, Lei T F, Wang Y G, Yao G L, Jiang Y H, Zhou K, Wang P, Zhang Z Y 2012 IEEE Trans. Electron Dev. 59 504
[14]	Luo X R, Fan J, Wang Y G, Lei T F, Qiao M, Zhang B, Udrea F 2011 IEEE Electron Dev. Lett. 32 185
[15]	Baba Y, Yanagiya S, Koshino Y, Udo Y 1994 Proceedings of the 6th International Power Semiconductor Devices and ICs Davos, Switzerland, May 31-June 2, 1994 p183
[16]	Kim S L, Yang H Y, Choi Y I 2000 Proceedings of the 22nd International Conference on Microelectronics Nis, Serbia, May 14-17, 2000 p641
[17]	Ge R, Luo X R, Jiang Y H, Zhou K, Wang P, Wang Q, Wang Y G, Zhang B, Li Z J 2012 J. Semicond. 33 074005
[18]	Zhang H P, Jiang L F, Sun L L, Li W J, Zhou L, Hua B X, Xu L Y, Lin M 2007 International Symposium on Communications and Information Technologies Sydney, Australia, October 17-19, 2007 p34

引用本文:

Citation:

计量

文章访问数: 1321
PDF下载量: 569
被引次数: 0

具有纵向漏极场板的低导通电阻绝缘体上硅横向双扩散金属氧化物半导体器件新结构

1. 天津大学电子信息工程学院, 天津 300072;

2. 天津理工大学电子信息工程学院, 天津 300384;

3. 电子科技大学微电子与固体电子学院, 成都 610054

基金项目:

国家自然科学基金（批准号：51101113）资助的课题.

收稿日期: 2013-12-22

修回日期: 2014-01-22

刊出日期: 2014-05-05

摘要: 为降低绝缘体上硅（SOI）横向双扩散金属氧化物半导体（LDMOS）器件的导通电阻，同时提高器件击穿电压，提出了一种具有纵向漏极场板的低导通电阻槽栅槽漏SOI-LDMOS器件新结构. 该结构特征为采用了槽栅槽漏结构，在纵向上扩展了电流传导区域，在横向上缩短了电流传导路径，降低了器件导通电阻；漏端采用了纵向漏极场板，该场板对漏端下方的电场进行了调制，从而减弱了漏极末端的高电场，提高了器件的击穿电压. 利用二维数值仿真软件MEDICI对新结构与具有相同器件尺寸的传统SOI结构、槽栅SOI结构、槽栅槽漏SOI 结构进行了比较. 结果表明：在保证各自最高优值的条件下，与这三种结构相比，新结构的比导通电阻分别降低了53%，23%和提高了87%，击穿电压则分别提高了4%、降低了9%、提高了45%. 比较四种结构的优值，具有纵向漏极场板的槽栅槽漏SOI结构优值最高，这表明在四种结构中新结构保持了较低导通电阻，同时又具有较高的击穿电压.

关键词:

A low on-resistance silicon on insulator lateral double diffused metal oxide semiconductor device with a vertical drain field plate

1.
School of Electronics Information Engineering, Tianjin University, Tianjin 300072, China;

2.
School of Electronics Information Engineering, Tianjin University of Technology, Tianjin 300384, China;

3.
School of Microelectronics and Solid-State Electronics, University of Electronic Science and Technology of China, Chengdu 610054, China

Fund Project:

Project supported by the National Natural Science Foundation of China (Grant No. 51101113).

Received Date: 22 December 2013

Accepted Date: 22 January 2014

Published Online: 05 May 2014

Abstract: To reduce the on-resistance and enhance the breakdown voltage of silicon on insulator (SOI) lateral double diffused metal oxide semiconductor (LDMOS) device at the same time, a low on-resistance SOI-LDMOS device with a vertical drain field plate and trench gate and trench drain (VFP-TGTD-SOI-LDMOS) is proposed. The device has the features as follows: first, a trench gate and a trench drain are adopted, which can widen the vertical current conduction area, shorten the lateral current conduction path, and lower the on-resistance. Secondly, a vertical field plate is used, which modulates the electric field around it, reduces the high electric field at the end of the drain electrode, and increases the breakdown voltage. The VFP-TGTD-SOI device is compared with a conventional SOI device, a trench gate SOI device, a trench gate and trench drain SOI device with the same dimensional device parameters using the two-dimensional semiconductor simulator MEDICI. The results show that under the condition of their own highest figure of merit (FOM), the specific on-resistance value of the VFP-TGTD-SOI device is reduced by 53%, 23%, and increased by 87%, respectively and the breakdown voltage is increased by 4% and reduced by 9% and increased by 45%, respectively. By comparing the FOMs of the four structures, it can be seen that the VFP-TGTD-SOI device has the highest FOM, which indicates that among the four structures, it maintains the lower on-resistance and holds the higher breakdown voltage at the same time.

Keywords:

全文HTML

参考文献 (18)

搜索

留言板