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Threshold voltage analytical model for strained Si SOI MOSFET with high-k dielectric

Li Jin Liu Hong-Xia Li Bin Cao Lei Yuan Bo

Threshold voltage analytical model for strained Si SOI MOSFET with high-k dielectric

Li Jin, Liu Hong-Xia, Li Bin, Cao Lei, Yuan Bo
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  • Abstract views:  3414
  • PDF Downloads:  716
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Publishing process
  • Received Date:  27 October 2009
  • Accepted Date:  06 February 2010
  • Published Online:  15 November 2010

Threshold voltage analytical model for strained Si SOI MOSFET with high-k dielectric

  • 1. Key Laboratory for Wide Band Gap Semiconductor Materials and Devices of Education,School of Microelectronics,Xidian University,Xi'an 710071,China

Abstract: A strained Si fully depleted SOI MOSFET,which has the advantages of strained Si,high-k gate and SOI structure, is presented in this paper. A two-dimensional analytical model for the threshold voltage in strained Si fully depleted SOI MOSFET with high-k dielectric is proposed by solving Possions equation. Several important parameters are taken into account in the model. Relationships between threshold voltage,Ge Profile and thickness of strained silicon are investigated. The result shows that the threshold voltage decreases with Ge Profile and strained silicon thickness increasing. Relationships between threshold voltage,dielectric constant of high k gate and doping conceration of strained silicon are also investigated. The result shows that the threshold voltage increases with dielectric constant of high-k and doping conceration of strained silicon increasing. SCE and DIBL are analyzed finally,which also demonstrate that this novel device can suppress SCE and DIBL effect greatly.

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