Characteristics of hydrogen terminated single crystalline diamond logic inverter

Xing Yu-Fei; Ren Ze-Yang; Zhang Jin-Feng; Su Kai; Ding Sen-Chuan; He Qi; Zhang Jin-Cheng; Zhang Chun-Fu; Hao Yue

doi:10.7498/aps.71.20211447

Abstract

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1. 引　言
2. Silvaco TCAD模拟基本方法描述与模型建立
3. 仿真结果与讨论
3.1 深能级缺陷对电阻率的影响
3.2 深能级缺陷对空间电荷分布特性及器件性能的影响
3.3 深能级缺陷浓度对空间电荷分布特性的影响
3.4 不同位置的深能级缺陷对空间电荷分布特性的影响
4. 结　论

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Abstract

Diamond has a wide band gap, high carrier mobility, and high thermal conductivity, thereby possessing great potential applications in high power, and high temperature electronics devices, and also inhigh temperature logic circuit. In this work, we fabricate a hydrogen terminated diamond metal-oxide-semiconductor field effect transistor (MOSFET) by using the atomic layer deposition grown Al₂O₃ as a gate dielectric and passivation layer. The device has a gate length and width of 4 μm and 50 μm, respectively. The device delivers a maximum output current of about 113.4 mA/mm at V_GS of –6 V and an ultra-high on/off ratio of 10⁹. In addition, we fabricate three resistors, respectively, with an interelectrode distance of 20, 80 and 160 μm, corresponding to the resistance value of 16.7, 69.5 and 136.4 kΩ, respectively. The logic inverter is realized by combining the MOSFET with the load resistance, and the characteristics of the logic inverter are demonstrated successfully, which indicates that the diamond MOSFET has great potential applications in future logic circuits.

Keywords:

PACS:

61.72.uj	(III-V and II-VI semiconductors)
61.72.-y	(Defects and impurities in crystals; microstructure)
85.25.0j

Authors and contacts

1.
The National Key Discipline Laboratory of Wide Band Gap Semiconductor, Xidian University, Xi’an 710071, China
2.
Wuhu Research Institute, Xidian University, Wuhu 241002, China

Corresponding author: Ren Ze-Yang, zeyangren@xidian.edu.cn

Funds: Project supported by the National Special Fund for Magnetic Confinement Nuclear Fusion Energy R&D Program (Grant No. 2019YFE03100200), the National Natural Science Foundation of China (Grant Nos. 62127812, 62004148, 61874080), the National Science and Technology Major Project of the Ministry of Science and Technology of China (Grant No. 2009ZYHW0015), the Natural Science Basic Research Program of Shanxi Province, China (Grant Nos. 2020JQ-315, 2018ZDCXL-GY-01-01-02, 2019ZDLGY16-02), and the China Postdoctoral Science Foundation (Grant No. 2021TQ0256).

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1. 引　言

CdZnTe晶体是近年发展起来的一种最具商业潜力的室温核辐射探测材料, 被广泛应用于制作高能物理、医学成像、工业探伤和核安全防护等领域的探测器和谱仪^[1-3]. 对于核医学应用的成像器件来说, 除了考虑缺陷对成像器件均匀性的影响外, 还面临着一个更大的挑战, 即在大计数率成像器件应用时, 要求探测器在200—2000 MHz/mm²脉冲X-ray的照射下具有优异的响应性能^[4]. CdZnTe探测器由于高的截止能量、室温工作特性以及在较低的辐射剂量下就可以具有较高的检测精度, 表现出更大的潜能^[5]. 美国的通用(GE)、荷兰的飞利浦(Philips)以及德国的西门子(Siemens)等国际著名的医疗器件厂商公司都已经开始设计与研制基于CdZnTe探测器的CT, PET和SPECT等核医学成像的设备^[6,7].

然而, 生长态CdZnTe晶体中不可避免地存在大量的杂质和缺陷, 诸如Cd空位、Te反位原子、Te间隙原子以及它们和杂质原子形成的缺陷复合体等^[8-10]. 这些结构缺陷容易形成载流子的陷阱, 在探测器工作时容易造成空间电荷积累, 引起电场畸变进而产生极化效应. 严重的极化效应甚至会使探测器彻底失效^[11,12]. 近年来的研究集中于观测CdZnTe晶体内电场分布特性以及测试大剂量照射下器件性能响应. Cola和Farella^[13]对CdTe晶体内部电场的研究表明, 空间电荷的积累会严重影响了电场分布, 进而降低了电荷收集效率. Li等^[14]研究了CdZnTe探测器在大剂量X射线照射下光电流特性对探测器性能的影响. Bale等^[15]、Camarda等^[16]和Musiienko等^[17]研究表明, 大剂量照射下积累的空间电荷会使探测器发生灾难性的故障. 对X射线成像系统来说, 空间电荷积累所引起电场的畸变是CdZnTe探测器面临的一大挑战^[18,19]. 然而, 目前对于深能级缺陷如何影响空间电荷分布的微观机制讨论较少. 如何在引入深能级缺陷使晶体实现高阻的同时, 尽可能避免深能级缺陷带来的不利影响, 是值得探索的一个问题. 因此, 系统掌握深能级缺陷对空间电荷分布特性的影响规律对提高器件的性能有着重要的意义. Silvaco TCAD仿真软件可以得到半导体内部电学性能等相关信息, 在半导体性质与器件性能仿真方面有突出优势^[20-22]. 由于晶体生长的复杂性且周期性长, 为了节约人力成本, 避免不必要的浪费, 本文采用Silvaco TCAD软件对CdZnTe晶体空间电荷分布等性质进行仿真, 探究深能级缺陷对空间电荷的分布以及内电场分布特性的影响规律, 从而揭示了深能级缺陷对器件性能的影响. 仿真结果将对CdZnTe晶体生长及成像器件的制备提供一定的理论指导.

2. Silvaco TCAD模拟基本方法描述与模型建立

Silvaco TCAD是以物理为基础对半导体特性进行设计和仿真的计算机辅助系统, 包含二维工艺仿真器Athena、二维器件仿真器件Atlas、器件编辑器Devedit和三维仿真器Victory. Atlas模拟是根据用户设定的物理参数来生成器件, 仿真半导体器件的电学、光学和热学特性等^[23]. 本文采用Silvaco TCAD对Au/CdZnTe/Au结构的探测器进行(two-dimensional, 2D)数值模拟, 研究CdZnTe晶体中深能级缺陷对空间电荷分布特性的影响规律. 仿真所用Au/CdZnTe/Au器件的结构示意图如图1(a)所示. 其中, CdZnTe晶体为N型半导体, 电子亲和能为4.3 eV. Au的功函数为5.1 eV, 具体的参数如表1所示. 本次模拟仿真采用三能级补偿模型^[24], 考虑晶体内部存在浅施主, 浅受主以及深施主能级, 如图1(b)所示. 同时定义, 浅施主能级的浓度为1.1 × 10¹² cm^–3, 浅受主能级的浓度为1.2 × 10¹² cm^–3, 浅施主与浅受主能级在室温下全电离. 普遍认为掺In的CdZnTe晶体中, 深施主能级( $\rm Te_{Cd}^{++}$ )能级位置为E_v + 0.86 eV^[25]. 非平衡载流子在该能级上会被俘获或者复合, 其电离后形成的空间电荷也会对电场分布特性产生一定影响, 从而影响着器件的性能. 为了研究不同深能级缺陷浓度对空间电荷分布特性的影响规律, 本文选用以下三种不同浓度的深能级信息作为仿真参数, 具体如表2所列.

$图 1 (a) Au/CdZnTe/Au器件结构示意图; (b) CdZnTe晶体内缺陷能级分布图\r\nFig. 1. (a) Schematic diagram of Au/CdZnTe/Au device structure; (b) distributions of defect energy levels in CdZnTe crystal.$

图 1 (a) Au/CdZnTe/Au器件结构示意图; (b) CdZnTe晶体内缺陷能级分布图

Fig. 1. (a) Schematic diagram of Au/CdZnTe/Au device structure; (b) distributions of defect energy levels in CdZnTe crystal.

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表 1 CdZnTe晶体的基本参数

Table 1. Basic parameters of CdZnTe crystals.

介电常数	300 K时禁带宽度/eV	300 K时导带密度/cm^–3	300 K时价带密度/cm^–3	电子迁移率/ cm²·V^–1·s^–1	空穴迁移率/cm²·V^–1·s^–1
10.9	1.6	9.14 × 10¹⁷	5.19 × 10¹⁸	1000	100

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表 2 深施主能级的基本信息

Table 2. Basic information of deep donor energy levels.

类型	位置/eV	浓度/cm^–3	电子俘获界面/cm²	空穴俘获界面/cm²	简并度
Donor1	E_v + 0.86	5 × 10¹²	3 × 10^–14	3 × 10^–15	2
Donor2	E_v + 0.86	1 × 10¹²	3 × 10^–14	3 × 10^–15	2
Donor3	E_v + 0.86	1 × 10¹³	3 × 10^–14	3 × 10^–15	2

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3. 仿真结果与讨论

3.1 深能级缺陷对电阻率的影响

不同深能级缺陷下仿真的CdZnTe晶体的电阻率结果如表3所列. 与不存在深能级缺陷的晶体相比, 深能级缺陷的加入会增大晶体的电阻率. 其原因是深施主去补偿多余的浅受主能级, 使载流子的浓度降低了, 费米能级也更靠近禁带中部位置, 从而使得电阻率增大^[25]. 而随着深能级缺陷浓度不断增加, 晶体的电阻率会随着该深能级缺陷的浓度增大而减小. 当深施主缺陷(E_v + 0.86 eV)浓度为5 × 10¹¹ cm^–3时, CdZnTe晶体的电阻率达到1.50 × 10¹⁰ Ω·cm, 满足探测器级CdZnTe晶体的电阻率要求.

表 3 不同深能级缺陷浓度下CdZnTe晶体的电阻率仿真结果

Table 3. The resistivity of CdZnTe crystals at different deep energy level concentrations via simulation.

能级类型	位置/eV	浓度/cm^–3	电阻率/Ω·cm
无深施主能级	—	—	6.08 × 10⁵
Donor1	E_v + 0.86	5 × 10¹¹	1.50 × 10¹⁰
Donor2	E_v + 0.86	1 × 10¹²	6.66 × 10⁹
Donor3	E_v + 0.86	1 × 10¹³	6.05 × 10⁸

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3.2 深能级缺陷对空间电荷分布特性及器件性能的影响

为了进一步研究深施主能级对CdZnTe晶体内部空间电荷以及内电场分布特性的影响规律, 本文选择深施主缺陷能级位置为E_v + 0.86 eV, 浓度为1 × 10¹² cm^–3条件下进行仿真, 其仿真结果如图2所示. CdZnTe晶体内部不同偏压下载流子浓度分布规律, 如图2(a)所示. 当外加偏压为0 V时, Au与CdZnTe界面处的载流子浓度低于体内的载流子浓度. 结合热平衡条件下Au/CdZnTe/Au的能带图(如图3(a)所示)可知, 当金属Au和n型CdZnTe晶体接触时, 因为金属Au的功函数大于半导体CdZnTe的功函数, 电子从半导体向金属流动, 金属的一侧聚集负电荷, 而半导体的一侧聚集正电荷. 积累的正电荷从半导体表面向内部延伸一定的厚度, 形成空间电荷区. 亦即Au与CdZnTe接触界面处存在一定的载流子耗尽区, 使得这部分电子的浓度低于CdZnTe晶体体内电子浓度. 与此同时, 空间电荷区的存在形成内建电场, 其电场的方向由半导体指向金属, 因而造成一定的能带弯曲. 随着外加偏压的增大, 晶体内载流子的浓度呈现出不均匀分布趋势. 这与外加偏压下Au/CdZnTe/Au能带倾斜有关. 如图3(b)所示, 当外加偏压大于0时, 由于外加电场的作用, Au/CdZnTe/Au能带发生由阴极向阳极逐渐倾斜的趋势, 从而使器件内载流子的浓度呈现不均匀分布.

$图 2 不同偏压下的Au/CdZnTe/Au器件仿真结果　(a) 载流子浓度分布; (b) 深施主的电离浓度分布; (c) 空间电荷浓度分布; (d) 内部电场强度分布变化规律\r\nFig. 2. Simulation results of Au/CdZnTe/Au device under different bias voltages: (a) Distribution of carrier concentration; (b) density of ionized deep donors; (c) distribution of space charge concentration; (d) distribution of internal electric field intensity.$

图 2 不同偏压下的Au/CdZnTe/Au器件仿真结果　(a) 载流子浓度分布; (b) 深施主的电离浓度分布; (c) 空间电荷浓度分布; (d) 内部电场强度分布变化规律

Fig. 2. Simulation results of Au/CdZnTe/Au device under different bias voltages: (a) Distribution of carrier concentration; (b) density of ionized deep donors; (c) distribution of space charge concentration; (d) distribution of internal electric field intensity.

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$图 3 Au/CdZnTe/Au器件内能带和内部电场分布示意图　(a) 热平衡的Au/CdZnTe/Au能带结构图; (b) U > 0的Au/CdZnTe/Au能带结构图; (c) 内部电场分布示意图\r\nFig. 3. Energy-band diagram and internal electric field distribution in Au/CdZnTe/Au device: (a) Au/CdZnTe/Au energy-band diagram in thermal equilibrium; (b) Au/CdZnTe/Au energy-band diagram under U > 0; (c) schematic diagram of internal electric field distribution.$

图 3 Au/CdZnTe/Au器件内能带和内部电场分布示意图　(a) 热平衡的Au/CdZnTe/Au能带结构图; (b) U > 0的Au/CdZnTe/Au能带结构图; (c) 内部电场分布示意图

Fig. 3. Energy-band diagram and internal electric field distribution in Au/CdZnTe/Au device: (a) Au/CdZnTe/Au energy-band diagram in thermal equilibrium; (b) Au/CdZnTe/Au energy-band diagram under U > 0; (c) schematic diagram of internal electric field distribution.

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载流子浓度的改变直接影响深能级的电离浓度^[26]. 图2(b)为不同偏压下, 深能级电离浓度的分布图. 晶体中深施主能级总浓度为1 × 10¹² cm^–3. 根据图2(b)仿真结果显示, 在热平衡下晶体内部已电离的深施主能级浓度约为1 × 10¹¹ cm^–3, 即大概有10%的深施主能级发生了电离. 与此同时, 根据仿真结果可得, 热平衡下晶体费米能级位于E_v + 0.9 eV, 深施主能级的位置为E_v + 0.86 eV. 因此, 热平衡下, 费米能级处于深能级上方, 深施主能级发生了部分电离. 未电离的深施主能级被电子所占据着, 呈现中性态. 其能带示意图如图3(a)所示. 由图2(b)可知, 晶体内阳极附近的区域, 同一个位置的深施主电离浓度随着外加偏压的增大而减小, 而其余的区域, 同一个位置的深施主电离浓度则随着外加偏压的增大而增大. 这可能与外加偏压作用下Au/CdZnTe/Au能带倾斜有关, 其趋势如图3(b)所示. 在倾斜的能带中, 深能级处于费米能级上方, 意味着深能级被电子占据的概率下降, 则深能级缺陷倾向于发射电子, 即深能级发生电离. 深施主能级电离后留下不可移动的正电中心, 聚集产生空间电荷区, 如图3(c)所示. 因此, 在外加偏压作用下, 晶体内空间电荷浓度分布也呈现阴极到阳极逐渐减小趋势, 且晶体中的空间电荷浓度随着外加偏压的增加而增大. 原因是晶体内部的空间电荷主要是来源于深施主能级的电离后的正电中心. 即外加偏压增大, 使得能带倾斜越厉害, 从而深施主电离的概率越大, 其空间电荷浓度也就越多. 由图2(c)可知, 在热平衡条件下空间电荷区约为50 μm. 当电压为100 V, 几乎整个探测器的体积都受到正空间电荷的影响. 与此同时, 随着外加电压的增大, 能带倾斜越厉害, 此时阳极区域的势垒不断下降. 因此, 阳极区域的空间电荷浓度随着外加电压的增大而减小.

器件内部空间电荷与电场关系满足如下泊松方程式:

$\begin{split} & - \frac{{{{\rm{d}}^{\rm{2}}}\varphi }}{{{\rm{d}}{x^2}}} = \frac{{{\rm{d}}E}}{{{\rm{d}}x}} = \frac{\rho }{{{\varepsilon _{\rm S}}}} \\ ={}& \frac{q}{{{\varepsilon _{\rm S}}}}(p + N_{{\rm{SD}}}^ + + N_{{\rm{DD}}}^ + - n - N_{{\rm{SA}}}^ - ), \end{split}$

(1)

式中, $\varphi$ 为静电势, E为电场, ${\varepsilon }_{\rm S}$ 为介电常数, ${N}_{\rm SD}^{+}$ 为已电离的浅施主能级浓度, ${N}_{\rm SA}^{-}$ 为已电离的浅受主能级浓度, ${N}_{\rm DD}^{+}$ 为已电离的深施主能级浓度, n(p)为自由电子(空穴)的浓度. 由泊松方程可得器件内电场强度分布, 如图2(d)所示. 当外加偏压大于0时, 内部电场强度分布由阴极向阳极逐渐减小的趋势, 深施主的电离率越大的区域, 其空间电荷浓度越大, 即内部电场越大. 与此同时, 阴极区域空间电荷所形成的内建电场与外加电场同向, 呈现三角形线性倾斜. 阳极区域空间电荷产生的内建电场与外加电场方向相反. 相互抵消后, 该区域电场强度特别弱, 形成死区. 死区对光生载流子的输运有较大的影响, 如图3(c)所示. 在死区中, 扩散是载流子唯一的驱动力. 这就增加了载流子在到达电极两端过程中被复合的概率, 从而使探测器的载流子收集效率降低.

综上, 外加电压时, Au/CdZnTe/Au器件整体的能带结构呈现由阴极向阳极逐渐倾斜的趋势, 且界面处能带弯曲对载流子的收集存在一定的影响. 随着外加电压逐渐增大, 阴极势垒逐渐增大, 越有利于空穴从半导体进入阴极, 即空穴在阴极很容易被收集; 与此同时, 阳极势垒不断降低, 越有利于电子从半导体进入阳极, 即电子在阳极很容易被收集. 随着外加电压的增大, 耗尽区的区域逐渐增大, 死区的区域在不断的减小, 越有利于探测器对载流子的收集.

3.3 深能级缺陷浓度对空间电荷分布特性的影响

晶体内部深能级缺陷的存在会对内电场分布产生较大影响. 为了进一步了解不同浓度的深能级缺陷对空间电荷分布特性及器件性能的影响规律, 仿真了位置为E_v + 0.86 eV, 深施主能级缺陷浓度分别为5 × 10¹¹, 1 × 10¹²和1 × 10¹³ cm^–3的CdZnTe探测器在100 V外加偏压下, 其空间电荷分布及内电场分布, 具体仿真结果如图4所示. 由图4(a)可以看出, 100 V偏压下Au/CdZnTe/Au器件内空间电荷分布呈现由阴极向阳极逐渐减小的趋势, 且在阳极区域附近空间电荷浓度很小, 近乎为0. 在阴极附近区域, 空间电荷的浓度随着深施主能级的浓度的增大而不断增大. 由图4(b)可知, 当深施主能级浓度为1 × 10¹³ cm^–3时, 内部电场变得陡峭. 在阴极区域电场强度很大, 且死区的区域最大. 这样的内部电场分布, 使得大部分的光生载流子(电子)无法通过漂移被阳极收集. 大量的电子在死区内只能靠浓度梯度扩散输运, 使得这部分载流子被晶体内部的缺陷俘获或者复合的概率急剧增大, 从而严重影响着探测器的载流子收集效率.

$图 4 100 V偏压下Au/CdZnTe/Au器件不同深施主浓度下的　(a) 空间电荷分布特性; (b) 内部电场分布特性\r\nFig. 4. Space charge distributions (a) and internal electric field distribution (b) of Au/CdZnTe/Au devices with different deep donor concentrations under bias of 100 V.$

图 4 100 V偏压下Au/CdZnTe/Au器件不同深施主浓度下的　(a) 空间电荷分布特性; (b) 内部电场分布特性

Fig. 4. Space charge distributions (a) and internal electric field distribution (b) of Au/CdZnTe/Au devices with different deep donor concentrations under bias of 100 V.

下载: 全尺寸图片幻灯片

3.4 不同位置的深能级缺陷对空间电荷分布特性的影响

为了得到不同位置的深能级缺陷对空间电荷分布特性及器件性能的影响规律. 本节仿真了CdZnTe晶体深施主能级缺陷浓度为1 × 10¹² cm^–3, 位置分别为E_v + 0.80, E_v + 0.82和E_v + 0.86 eV时, 且在100 V外加偏压下其内部空间电荷分布及内电场分布图, 仿真结果如图5所示. 由仿真得到深施主能级位于E_v + 0.80, E_v + 0.82和E_v + 0.86 eV时, 晶体的电阻率分别为6.85 × 10¹⁰, 3.19 × 10¹⁰和6.66 × 10⁹ Ω·cm, 都满足探测器级CdZnTe晶体的电阻率要求. 由图5(a)可知, 在100 V的偏压下, 阴极区域附近的空间电荷浓度随着深施主能级位置的增大而增大, 而阳极区域和阴极区域的相反. 原因是深施主能级位置越接近于导带, 如上文所述在外加偏压作用时, 能带发生倾斜, 其深施主能级缺陷的电离浓度就越大. 且位置为E_V + 0.86 eV的施主能级在阳极附近的出现空间电荷近乎为0的区域. 由图5(b)可知, 当深施主能级位置为E_V + 0.80 eV时, 内部电场较平坦, 在阴极区域的电场强度最小, 且无死区的区域. 亦即在100 V的偏压下, 器件完全工作在耗尽层内, 则光生载流子就可以通过漂移的方式快速地到达两端的电极, 从而大大减小在输运过程中被俘获或者复合的概率, 进而提升了载流子的收集效率.

$图 5 100 V偏压下Au/CdZnTe/Au器件不同深施主位置下的　(a) 空间电荷分布特性; (b)内部电场分布特性\r\nFig. 5. Space charge distributions (a) and internal electric field distribution (b) of Au/CdZnTe/Au devices with different depths of deep donor under bias of 100 V.$

图 5 100 V偏压下Au/CdZnTe/Au器件不同深施主位置下的　(a) 空间电荷分布特性; (b)内部电场分布特性

Fig. 5. Space charge distributions (a) and internal electric field distribution (b) of Au/CdZnTe/Au devices with different depths of deep donor under bias of 100 V.

下载: 全尺寸图片幻灯片

4. 结　论

本文采用半导体器件仿真软件TCAD系统分析了CdZnTe晶体内深能级缺陷浓度、位置以及外加偏压对空间电荷分布特性及器件性能的影响. 仿真结果表明当增大器件的外加偏压时, Au/CdZnTe/Au结构整体的能带结构呈现由阴极下阳极逐渐倾斜的趋势. 晶体内的空间电荷浓度随着外加偏压的增加而增大, 死区逐渐减小, 从而大大降低光生的载流子被俘获或者复合的概率, 进而有助于提高器件中载流子的收集效率. 在保证CdZnTe晶体电阻率高阻为前提下, 位于E_V + 0.86 eV的深能级缺陷, 其浓度降低为5 × 10¹¹ cm^–3时, 阴极附近区域的空间电荷浓度降低, 死区减小, 晶体内部电场更加平坦, 进而有助于提升载流子的收集效率. 与此同时, 当深能级位置为E_V + 0.80 eV时, 内部电场较平坦, 且无死区存在. 亦即在100 V的偏压下, 器件可完全工作在耗尽层内, 则光生载流子就可以通过漂移的方式快速地到达两端的电极, 从而大大减小在输运过程中被俘获或者复合的概率, 进而提升载流子的收集效率.

References

[1]	Wort C J H, Balmer R S 2008 Mater. Today 11 22 Google Scholar
[2]	Baliga B J 1989 IEEE Electr. Device Lett. 10 455 Google Scholar
[3]	Achard J, Silva F, Tallaire A, Bonnin X, Lombardi G, Hassouni K, Gicquel A 2007 J. Phys. D:Appl. Phys. 40 6175 Google Scholar
[4]	Kasu M, Ueda K, Ye H, Yamauchi Y, Sasaki S, Makimoto T 2006 Diam. Relat. Mater. 15 783 Google Scholar
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[17]	Ren Z, Lv D, Xu J, Zhang J, Zhang J, Su K, Zhang C, Hao Y 2020 Appl. Phys. Lett. 116 013503 Google Scholar
[18]	Liu J W, Liao M Y, Imura M, Watanabe E, Oosato H, Koide Y 2014 Appl. Phys. Lett. 105 082110 Google Scholar
[19]	Liu J W, Oosato H, Liao M Y, Imura M, Watanabe E, Koide Y 2018 Appl. Phys. Lett. 112 153501 Google Scholar
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[23]	Yamaguchi T, Umezawa H, Ohmagari S, Koizumi H, Kaneko J H 2021 Appl. Phys. Lett. 118 162105 Google Scholar
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图 1 实验制备器件的原理图　(a) 剖面图; (b) 俯视图

Figure 1. Schematic diagram of the device structure: (a) Sectional view; (b) top view.

DownLoad: Full-Size Img PowerPoint

图 2 器件负载电阻　(a) I-V特性; (b) R₁, R₂, R₃电阻阻值

Figure 2. The load resistance of device: (a) I-V relationships; (b) resistance values for the R₁, R₂ and R₃ resistors.

DownLoad: Full-Size Img PowerPoint

图 3 氢终端金刚石MOSFET器件输出特性

Figure 3. Output characteristics of the hydrogen-terminated diamond (H-diamond) MOSFET.

DownLoad: Full-Size Img PowerPoint

图 4 氢终端金刚石MOSFET器件传输特性

Figure 4. Transfer characteristics of the H-diamond MOSFET.

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图 5 不同负载电阻的逻辑反相器的电压传输特性

Figure 5. The voltage transfer characteristics of the logic inverter with the various load resistors.

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图 6 反相器不同负载电阻情况下增益与输入电压的关系

Figure 6. Relationship between V_in and the gain of the inverter under different load resistances.

DownLoad: Full-Size Img PowerPoint

图 7 (a)恒流区器件输出电压变化; (b)可变电阻区器件输出电压变化

Figure 7. (a) Output voltage variation in saturation area; (b) output voltage variation in variable resistance area.

DownLoad: Full-Size Img PowerPoint

表 1 不同条件沉积的Al₂O₃介质的氢终端金刚石MOSFET器件的最大输出电流密度

Table 1. Summarization of the characterization of the H-diamond MOSFETs with the different temperatures grown Al₂O₃ as gate dielectrics.

Al₂O₃厚度/nm	生长温度/℃	L_G/μm	L_GD/μm	电流密度/(mA·mm^–1)	参考文献
6	80	0.1	—	585.0	[8]
20	200	2.0	2	339.0	[14]
20	300	2.0	2	85.0	[14]
25	300	2.0	2	339.0	[17]
83	450	5.0	20	12.0	[23]
200	450	20.0	10	18.2	[24]
200	450	2.0	17	120.0	[25]
200	450	6.0	6	12.0	[6]
200	450	15.0	24	5.2	[10]
400	450	2.0	17	59.0	[26]
15	300	4.0	2	113.4	本工作

DownLoad: CSV

[1]	Wort C J H, Balmer R S 2008 Mater. Today 11 22 Google Scholar
[2]	Baliga B J 1989 IEEE Electr. Device Lett. 10 455 Google Scholar
[3]	Achard J, Silva F, Tallaire A, Bonnin X, Lombardi G, Hassouni K, Gicquel A 2007 J. Phys. D:Appl. Phys. 40 6175 Google Scholar
[4]	Kasu M, Ueda K, Ye H, Yamauchi Y, Sasaki S, Makimoto T 2006 Diam. Relat. Mater. 15 783 Google Scholar
[5]	Hirama K, Sato H, Harada Y, Yamamoto H, Kasu M 2012 IEEE Electr. Device Lett. 33 1111 Google Scholar
[6]	Kawarada H, Tsuboi H, Naruo T, Yamada T, Xu D, Daicho A, Saito T, Hiraiwa A 2014 Appl. Phys. Lett. 105 4 Google Scholar
[7]	Liu J, Yu H, Shao S, Tu J, Zhu X, Yuan X, Wei J, Chen L, Ye H, Li C 2020 Diam. Relat. Mater. 104 107750 Google Scholar
[8]	Yu X X, Zhou J J, Qi C J, Cao Z Y, Kong Y C, Chen T S 2018 IEEE Electr. Device Lett. 39 1373 Google Scholar
[9]	Ueda K, Kasu M, Yamauchi Y, Makimoto T, Schwitters M, Twitchen D J, Scarsbrook G A, Coe S E 2006 IEEE Electr. Device Lett. 27 570 Google Scholar
[10]	Kitabayashi Y, Kudo T, Tsuboi H, Yamada T, Xu D, Shibata M, Matsumura D, Hayashi Y, Syamsul M, Inaba M, Hiraiwa A, Kawarada H 2017 IEEE Electr. Device Lett. 38 363 Google Scholar
[11]	Imanishi S, Horikawa K, Oi N, Okubo S, Kageura T, Hiraiwa A, Kawarada H 2019 IEEE Electr. Device Lett. 40 279 Google Scholar
[12]	Russell S A O, Sharabi S, Tallaire A, Moran D A J 2012 IEEE Electr. Device Lett. 33 1471 Google Scholar
[13]	Kasu M, Ueda K, Ye H, Yamauchi Y, Sasaki S, Makimoto T 2005 IEEE Electr. Device Lett. 41 1249 Google Scholar
[14]	Ren Z Y, Yuan G S, Zhang J F, Xu L, Zhang J C, Chen W J, Hao Y 2018 Aip. Adv. 8 6 Google Scholar
[15]	Daicho A, Saito T, Kurihara S, Hiraiwa A, Kawarada H 2014 J. Appl. Phys. 115 4 Google Scholar
[16]	Wang Y F, Chang X, Zhang X, Fu J, Fan S, Bu R, Zhang J, Wang W, Wang H X, Wang J 2018 Diam. Relat. Mater. 81 113 Google Scholar
[17]	Ren Z, Lv D, Xu J, Zhang J, Zhang J, Su K, Zhang C, Hao Y 2020 Appl. Phys. Lett. 116 013503 Google Scholar
[18]	Liu J W, Liao M Y, Imura M, Watanabe E, Oosato H, Koide Y 2014 Appl. Phys. Lett. 105 082110 Google Scholar
[19]	Liu J W, Oosato H, Liao M Y, Imura M, Watanabe E, Koide Y 2018 Appl. Phys. Lett. 112 153501 Google Scholar
[20]	Liu J, Ohsato H, Liao M, Imura M, Watanabe E, Koide Y 2017 IEEE Electr. Device. Lett. 38 922 Google Scholar
[21]	Wang J J, He Z Z, Yu C, Song X B, Xu P, Zhang P W, Guo H, Liu J L, Li C M, Cai S J, Feng Z H 2014 Diam. Relat. Mater. 43 43 Google Scholar
[22]	Ren Z, Zhang J, Zhang J, Zhang C, Xu S, Li Y, Hao Y 2017 IEEE Electr. Device Lett. 38 786 Google Scholar
[23]	Yamaguchi T, Umezawa H, Ohmagari S, Koizumi H, Kaneko J H 2021 Appl. Phys. Lett. 118 162105 Google Scholar
[24]	Inaba M, Muta T, Kobayashi M, Saito T, Shibata M, Matsumura D, Kudo T, Hiraiwa A, Kawarada H 2016 Appl. Phys. Lett. 109 033503 Google Scholar
[25]	Kawarada H, Yamada T, Xu D, Kitabayashi Y, Shibata M, Matsumura D, Kobayashi M, Saito T, Kudo T, Inaba M, Hiraiwa A, Ieee. 2016 Diamond MOSFETs using 2D Hole Gas with 1700 V Breakdown Voltage. (New York: Ieee) p483
[26]	Syamsul M, Kitabayashi Y, Kudo T, Matsumura D, Kawarada H 2017 IEEE Electr. Device. Lett. 38 607 Google Scholar

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