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The holding voltage of electrostatic discharge (ESD) protecting structure is the critical parameter to determine the latch-up performance of the protecting device, but the thermal change of ESD device parameters lead the protecting device to suffer latch-up risk at high ambient temperature. In this paper, the holding characteristics of the ESD protecting device at various ambient temperatures ranging from 30 ℃ to 195 ℃ are studied. The investigated ESD structure is the N-channel metal oxide semiconductor (NMOS) transistors fabricated with the 0.18 μm partially depleted silicon-on-insulator process. The ESD characteristics of the device are measured by the transmission line pulse test system at different ambient temperatures. The test results show that the holding voltage (VH) decreases with temperature increasing. The TCAD simulation is carried out to support and analyze the experimental results, and the same trend of VH versus temperature is obtained. Through the analysis of simulation results and theoretical derivation, the underlying physical mechanisms related to the effects of temperature on VH and holding current (IH) are discussed in detail. When the drain is subjected to the same current pulsing and the Source and Body are both grounded, the distributions of current density, electric potential, and injected electron density of NMOS at various temperatures are extracted and analyzed. When the Drain, Source, and Body are all grounded, the distributions of the electrostatic field at various temperatures are extracted and analyzed. The distribution of electric potential in NMOS indicates that the voltage drop on the Drain-Body junction (VDB) is affected by ambient temperature significantly, and the variation of VDB dominates the variation trend of VH with temperature increasing. The reducing electrostatic field and increasing injected electron density with temperature decreasing contribute to the decreasing of VDB. The trend of IH and parasitic Body resistance (RBody) weakens the temperature dependence of the VH. The current gain of parasitic bipolar transistor (β) decreases with ambient temperature rising, which is the main contributor to the decreasing of IH. Therefore, increasing IH and RBody is helpful in reducing the temperature dependence of the latch-immune ESD protection structure.
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Keywords:
- electrostatic discharge /
- metal-oxide-semiconductor field-effect transistor /
- holding voltage /
- high temperature
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Google Scholar
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Google Scholar
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Google Scholar
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Google Scholar
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Google Scholar
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Google Scholar
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Google Scholar
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Google Scholar
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Google Scholar
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Google Scholar
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Google Scholar
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图 1 不同温度下GTNMOS的ESD I-V曲线. 插图为曲线维持处的细节
Figure 1. The ESD I-V curves of NMOS under different temperatures. Insert: the detail in holding points.
图 2 不同温度下, (a) GTNMOS和(b) GGNMOS的TCAD仿真ESD I-V曲线, 插图为曲线维持处的细节
Figure 2. The TCAD simulated ESD I-V curves of (a) GTNMOS and (b) GGNMOS under different temperatures, where the insert is the detail in holding points.
图 3 不同温度下GTNMOS的TLP测试结果与TCAD仿真结果对比
Figure 3. The TLP tested holding voltage and TCAD simulated holding voltage under various ambient temperatures.
图 4 PDSOI NMOS器件截面图及作为ESD防护器件工作时的工作机制示意图
Figure 4. Cross-sectional view and the equivalent circuit of the PDSOI NMOS.
图 5 施加相同ESD电流脉冲的GGNMOS在不同温度下静电势分布
Figure 5. Electrostatic potential distributions of GGNMOS under various ambient temperatures when the Drain is subject to the same ESD current pulsing. The Source and the Body are grounded.
图 6 施加相同ESD电流脉冲的GGNMOS在不同温度下的源-体界面位置 (沿Path 1路径) 的静电势分布曲线
Figure 6. Electrostatic potential distributions in the drain-body surface of GGNMOS along path 1 under various ambient temperatures when the drain is subject to the same ESD current pulsing. The Source and the Body are grounded.
图 7 不施加ESD电流脉冲的GGNMOS在不同温度下的电场分布
Figure 7. Electric field distributions of GGNMOS under various ambient temperatures when the drain, the source and the body are grounded.
图 8 施加相同ESD电流脉冲的GGNMOS在不同温度下的电子浓度分布
Figure 8. Electron density distributions of GGNMOS under various temperatures when the drain is subjected to the same ESD current pulsing. The source and the body are grounded.
图 9 施加相同ESD电流脉冲的GGNMOS在不同温度下的源-体结界面位置 (沿Path 2路径) 的静电势分布
Figure 9. Electrostatic Potential distributions in the drain-source surface of GGNMOS along path 2 under various temperatures when the Drain is subjected to the same ESD current pulsing. The Source and the Body are grounded.
图 10 施加相同ESD电流脉冲的GGNMOS在不同温度下的电流密度分布
Figure 10. Current density distributions of GGNMOS under various temperatures when the drain is subjected to the same ESD current pulsing. The Source and the Body are grounded.
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[1] Bafleur M, Caignet F, Nolhier N, 2017 ESD Protection Methodologies (Amsterdam, Holland: Elsevier) xvii
[2] Vinson J E, Liou J J 1998 Proc. IEEE 86 399
Google Scholar
[3] Duvvury C, Amerasekera A 1993 Proc. IEEE 81 690
Google Scholar
[4] Ker M D 1999 IEEE Trans. Electron. Devices 46 173
Google Scholar
[5] Ker M D, Hsu C K 2005 IEEE Trans. Device Mater. Reliab. 5 235
Google Scholar
[6] Voldman S H 2008 LATCHUP (Hoboken, New Jersey: John Wiley & Sons) p1
[7] Boselli G, Duvvury C 2005 Microelectron. Reliab. 45 1406
Google Scholar
[8] Voldman S H 2005 Microelectron. Reliab. 45 437
Google Scholar
[9] Wang A 2002 On-chip ESD Protection for Integrated Circuits: An IC Design Perspective (Boston, MA: Springer) p1
[10] Ker M, Wu C Y, Chang H H 1996 IEEE Trans. Electron. Devices 43 588
Google Scholar
[11] Li C, Zhang F, Wang C K, Chen Q, Lu F, Wang H, Di M F, Cheng Y H, Zhao H J, Wang A 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) Qingdao, China 2018 p743
[12] Wang J X, Li X J, Zhao F Z, Zeng C B, Li D L, Li L C, Li J J, Li B, Han Z S, Luo J J 2021 Chin. Phys. B 30 078501
Google Scholar
[13] Wang J X, Zhao F Z, Ni T, Li D L, G L C, Wang J J, Li X J, Zeng C B, Luo J J, Han Z S 2021 Microelectron. Reliab. 126 114239
Google Scholar
[14] Tazzoli A, Marino F A, Cordoni M, Benvenuti A, Colombo P, Zanoni E, Meneghesso G 2007 Microelectron. Reliab. 47 1444
Google Scholar
[15] Won J I, Lee H D, Lee K Y, Kim K D, Koo Y S 2009 IEEE Region 10 Conference 2009 Singapore, 2009 p2553
[16] Jang S L, Lin S L 2000 Solid-State Electron. 44 2139
Google Scholar
[17] Liang W, Dong A, Li H, Miao M, Kuo C C, Klebanov M, Liou J J 2016 Microelectron. Reliab. 66 46
Google Scholar
[18] Meneghesso G, Tazzoli A, Marino F A, Cordoni M, Colombo P 2008 46 th Annual IEEE International Reliability Physics Symposium Phoenix 2008 p3
[19] Hou F, Liu J Z, Liu Z W, Huang W, Gong T X, Liou J J 2019 IEEE Trans. Electron Devices 66 2044
Google Scholar
[20] Do K I, Jin H S, Lee B S, Koo Y S 2021 IEEE J. Electron Devices Soc. 9 1017
Google Scholar
[21] Wu M, Lu W Z, Zhang C C, Peng W, Zeng Y, Jin H, Xu J, Chen Z J 2020 Semicond. Sci. Technol. 35 045016
Google Scholar
[22] Li S S 1978 Solid-State Electron. 21 1109
Google Scholar
[23] Khanna V K 2017 Extreme-Temperature and Harsh-Environment Electronics: Physics, Technology and Applications (Boca Raton: CRC Press)
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