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高k介质电导增强SOI LDMOS机理与优化设计

王骁玮 罗小蓉 尹超 范远航 周坤 范叶 蔡金勇 罗尹春 张波 李肇基

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高k介质电导增强SOI LDMOS机理与优化设计

王骁玮, 罗小蓉, 尹超, 范远航, 周坤, 范叶, 蔡金勇, 罗尹春, 张波, 李肇基

Mechanism and optimal design of a high-k dielectric conduction enhancement SOI LDMOS

Wang Xiao-Wei, Luo Xiao-Rong, Yin Chao, Fan Yuan-Hang, Zhou Kun, Fan Ye, Cai Jin-Yong, Luo Yin-Chun, Zhang Bo, Li Zhao-Ji
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  • 本文提出一种高k介质电导增强SOI LDMOS新结构(HK CE SOI LDMOS),并研究其机理. HK CE SOI LDMOS的特征是在漂移区两侧引入高k介质,反向阻断时,高k介质对漂移区进行自适应辅助耗尽,实现漂移区三维RESURF效应并调制电场,因而提高器件耐压和漂移区浓度并降低导通电阻. 借助三维仿真研究耐压、比导通电阻与器件结构参数之间的关系. 结果表明,HK CE SOI LDMOS与常规超结SOI LDMOS相比,耐压提高16%–18%,同时比导通电阻降低13%–20%,且缓解了由衬底辅助耗尽效应带来的电荷非平衡问题.
    A high-k dielectric conduction enhancement SOI LDMOS is proposed and investigated by simulation. The high-k dielectric pillars are located at sidewalls of the drift region. The high-k dielectric assists the self-adapted depletion in the drift region, reshapes the electric field distribution, and makes the three-dimensional RESURF effect realized in a high-voltage blocking state. Dependences of the breakdown voltage (VB) and the specific on-resistance (Ron,sp) on device parameters are exhibited using three-dimensional simulation. Simulation results show that the proposed structure increases VB by 16%–18% and decreases Ron.sp by 13%–20%, compared with the conventional super-junction SOI LDMOS. Furthermore, the charge-imbalance caused by the substrate-assisted depletion effect is alleviated.
    • 基金项目: 国家自然科学基金(批准号:61176069)、中国博士后科学基金(批准号:2012T50771)和教育部新世纪优秀人才支持计划(批准号:NCET-11-0062)资助的课题.
    • Funds: Project supported by the National Natural Science Foundation of China (Grant No. 61176069), China Postdoctoral Science Foundation (Grant No. 2012T50771), and the Program for New Century Excellent Talents in University of Ministry of Education of China (Grant No. NCET-11-0062).
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  • [1]

    Zhang B, Luo X R, Li Z J 2010 Chin. Phys. B 19 037303

    [2]

    Zhang B, Hu S D, Li Z J 2009 Chin. Phys. B 18 319

    [3]

    Li Z J, Zhang B, Li Q 2007 Acta Phys. Sin. 56 6660 (in Chinese) [李肇基, 张波, 李琦 2007 物理学报 56 6660]

    [4]

    Chen X B, Mawby P A, Board K, Salama C A T 1998 Microelectron J. 29 1005

    [5]

    Nassif-Khalil S G, Salama C A T 2002 ISPSD 1 81

    [6]

    Pathirana G P V, Udrea F, Ng R, Garner D M, Amaratunga G A J 2003 ISPSD 1 278

    [7]

    Xu S, Gan K P, Samudra G S, Liang Y C, O J K 2000 IEEE Trans Electron Devices 47 1980

    [8]

    Amberetu M A, Salama C A T 2002 ISPSD 1 101

    [9]

    Nassif-Khalil S G, Salama C A T 2003 IEEE Tran. Electron Devices 50 1385

    [10]

    Nassif-Khalil S G, Salama C A T 2003 ISPSD 1 228

    [11]

    Chen Y, Liang Y C, Samudra G S 2006 IEEE Industrial Electronics 32 2746

    [12]

    Chen X 2007 U S Patent 7230310B2 1 1

    [13]

    Luo X R, Jiang Y H, Zhou K, Wang P, Wang X W, Wang Q, Yao G L, Zhang B, Li Z J 2012 IEEE Electron Device Letters 33 1042

    [14]

    Luo X R, Cai J Y, Fan Y, Fan Y H, Wang X W, Wei J, Jang Y H, Zhou K, Yin C, Zhang B, Li Z J, Hu G Y 2013 IEEE Electron Device Letters 60 2840

    [15]

    Pontes M, Lee E J H, Leite E R, Longo E, Varela J A 2000 J. Mater Sci. 35 4783

    [16]

    Wang Z, Kugler V, Helmersson U, Konofaos N, Evangelou E K, Nakao S, Jin P 2001 Appl Phy. Lett. 79 1513

计量
  • 文章访问数:  1862
  • PDF下载量:  521
  • 被引次数: 0
出版历程
  • 收稿日期:  2013-07-15
  • 修回日期:  2013-09-17
  • 刊出日期:  2013-12-05

高k介质电导增强SOI LDMOS机理与优化设计

  • 1. 电子科技大学微电子与固体电子学院, 成都 610054
    基金项目: 

    国家自然科学基金(批准号:61176069)、中国博士后科学基金(批准号:2012T50771)和教育部新世纪优秀人才支持计划(批准号:NCET-11-0062)资助的课题.

摘要: 本文提出一种高k介质电导增强SOI LDMOS新结构(HK CE SOI LDMOS),并研究其机理. HK CE SOI LDMOS的特征是在漂移区两侧引入高k介质,反向阻断时,高k介质对漂移区进行自适应辅助耗尽,实现漂移区三维RESURF效应并调制电场,因而提高器件耐压和漂移区浓度并降低导通电阻. 借助三维仿真研究耐压、比导通电阻与器件结构参数之间的关系. 结果表明,HK CE SOI LDMOS与常规超结SOI LDMOS相比,耐压提高16%–18%,同时比导通电阻降低13%–20%,且缓解了由衬底辅助耗尽效应带来的电荷非平衡问题.

English Abstract

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