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本文提出了一种具有双漂移区和双导通路径的新型LDMOS器件，实现了超低比导通电阻Ron,sp。其特点在于，漂移区采用P型和N型纵向交替所构成的双漂移区结构，并引入平面栅和槽型栅分别控制P型和N型漂移区，使得器件能够在漂移区中形成两条独立的电子导通或消失路径。在对平面栅施加正向电压时，可使P型漂移区的表面发生反型，形成连接沟道和N+漏极的高浓度电子反型层，从而极大提高器件导通时的电子密度，降低比导通电阻。槽型栅极的引入可使器件在关断时产生一条额外的电子消失路径，从而缩短器件的关断时间toff。此外，由于引入P型漂移区，使得电子在P型漂移区内输运时与其体内的空穴发生复合，从而加快了电子的消失过程并进一步地缩短器件的toff。仿真结果表明，在200V的击穿电压BV等级下，本文所提出的新型LDMOS的Ron,sp为3.43mΩ·cm2，关断时间为9ns。相比传统的LDMOS器件，Ron,sp和toff分别下降了90%，11.6%。该器件不仅实现了Ron,sp和BV的良好折中，而且缩短了器件的toff，展现出了优异的器件性能。In order to improve the contradictory between Specific On-resistance (Ron,sp) and Breakdown voltage (BV) of LDMOS, and enhance the turn-off characteristic, this paper proposes a novel LDMOS device with dual-drift regions and dual-conduction paths, which achieves an ultra-low Ron,sp. The key feature of the proposed device is the introduction of a dual-drift region structure with alternating P-type and N-type regions, along with the incorporation of planar and trench gates to control the P-type and N-type drift regions, respectively. This configuration enables the formation of two independent electron conduction paths within the drift region. When a positive voltage is applied to the planar gate, a voltage difference generated between the surface of the P-type drift region and the body of device’s drift. Thereby, under the impact of the voltage difference, the electrons are pulled to the surface of the P-type drift region to inverts and forms a high-density electron inversion layer that connects the channel and the N+ drain, which significantly increases the electron density during conduction and reduces the Ron,sp. The introduction of the trench gate provides an additional electron disappearance path, which shortens the device's turn-off time (toff). Furthermore, the introduction of the P-type drift region facilitates the recombination of electrons with holes within the P-type drift region, accelerating the electron disappearance process and further reducing the device'stoff. What’s more, the proposed device exhibits a more uniform electric field distribution and higher voltage capability is due to the P+N-N+P+ structure adopted in the PolySi-top layer. During the off-state, each of the P+N- junction and the N+P+ junction generate an electric field peak at the interface, which modulates the electric field distribution on the surface of the drift region. Simulation results indicate that at a Breakdown Voltage (BV) level of 200V, the proposed LDMOS exhibits a Ron,sp of 3.43 mΩ·cm² and a toff of 9 ns. Compared to conventional LDMOS devices, there is a 90% reduction in Ron,sp and an 11.6% decrease in toff. The proposed device not only achieves an excellent trade-off between Ron,sp and BV but also shortens the toff, demonstrating the device achieved superior performance.
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Keywords:
- Dual-drift /
- Dual-conduction paths /
- Specific on-resistance /
- Breakdown voltage
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[1] Kong M, Yi B, Zhang B 2019IEEE Trans. Electron Devices 66 592
[2] Disney D, Chan W, Lam R, Blattner R, Ma S, Seng W, Chen J W, Cornell M, Williams R 2008 20th International Symposium on Power Semiconductor Devices and IC’s, 2008-05 pp24–27
[3] Sun W, Shi L, Sun Z, Yi Y, Li H, Lu S 2006IEEE Trans. Electron Devices 53 891
[4] Erlbacher T, Bauer A J, Frey L 2010IEEE Electron Device Lett. 31 464
[5] Qiao M, Li Y, Zhou X, Li Z, Zhang B 2014IEEE Electron Device Lett. 35 774
[6] Baliga B J 2001Proc. IEEE 89 822
[7] Efland T R, Tsai C Y, Pendharkar S 1998International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217), 1998-12 pp679–682
[8] Li M, Chen D, Jung D S, Shi X 20192019 China Semiconductor Technology International Conference, 2019-03 pp1–3
[9] Baliga B J 2023Springer Handbook of Semiconductor Devices Cham, 2023 pp491–523
[10] Baliga B J 2019 Fundamentals of Power Semiconductor Devices (Cham: Springer International Publishing)
[11] Appels J A, Vaes H M J 19791979 International Electron Devices Meeting, 1979-12 pp238–241
[12] Hossain Z 2008200820th International Symposium on Power Semiconductor Devices and IC’s, 2008-05 pp133–136
[13] Xiarong H, Bo Z, Xiaorong L, Guoliang Y, Xi C, Zhaoji L 2011J. Semicond. 32 074006
[14] Hardikar S, Tadikonda R, Green D W, Vershinin K V, Narayanan E M S 2004IEEE Transactions on Electron Devices 51 2223
[15] Stengl R, Gosele U 19851985 International Electron Devices Meeting, 1985-12 pp154–157
[16] Duan B, Xing L, Wang Y, Yang Y 2022IEEE Trans. Electron Devices 69 658
[17] Chen Y, Hu S, Cheng K, Jiang Y, Luo J, Wang J, Tang F, Zhou X, Zhou J, Gan P 2016Superlattices and Microstructures 89 59
[18] Fujihira T 1997Jpn. J. Appl. Phys. 36 6254
[19] Chen X B 2000CHINESE JOURNAL OF ELECTRONICS 9 6
[20] Baliga B J, Syau T, Venkatraman P 1992IEEE Electron Device Lett. 13 427
[21] Wang Y, Duan B, Song H, Yang Y 2021IEEE Trans. Electron Devices 68 2414
[22] Inc. Synopsys 2016 SentaurusTM Device User Guide Verison L-2016.03
[23] Chen W, Qin H, Zhang H, Han Z 2022IEEE Trans. Electron Devices 69 1900
[24] Zhou K, Luo X, Li Z, Zhang B 2015IEEE Trans. Electron Devices 62 3334
[25] Cao Z, Sun Q, Zhang H, Wang Q, Ma C, Jiao L 2022Micromachines 13 843
[26] Cheng J, Zhang B, Li Z 2008IEEE Electron Device Letters 29 645
[27] Chen Y M, Lee C L, Tsai M H, Lee C T, Wang C C 20182018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs, 2018-05 pp331–334
[28] Zhang S, Tuan H C, Wu X J, Shi L, Wu J 2016Microelectron. Reliab. 61 125
[29] Chen W, Pjencak J, Agam M, Janssens J, Jerome R, Menon S, Griswold M 2021202133rd International Symposium on Power Semiconductor Devices and ICs, 2021-05 pp287–290
[30] Qiao M, Liu W, Yuan L, Xu P, Ma C, Lin F, Liu K, Guo Y, Lin Z, Zhang S, Zhang B 20222022 IEEE 34th International Symposium on Power Semiconductor Devices and ICs, 2022-05-22 pp149–152
[31] Kong M, Yi B, Chen X 20192019 IEEE 13th International Conference on Power Electronics and Drive Systems, 2019-07 pp1–4
[32] Fan J, Wang Z G, Zhang B, Luo X R 2013 Chin. Phys. B 22 048501
[33] Honarkhah S, Nassif-Khalil S, Salama C A T 2004Proceedings of the 30th European Solid-State Circuits Conference, 2004-09 pp117–120
[34] Hölke A, Antoniou M, Udrea F 202032nd International Symposium on Power Semiconductor Devices and ICs, 2020-09 pp435–438
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