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半导体量子点作为量子比特的载体, 因具有扩展性好[1]、容易实现初始化[2,3]及可以对量子比特状态进行精确读出[4]等优点而得到了人们日益增加的关注. 最初量子点自旋量子比特的研究集中在砷化镓[5]、砷化铟[6]等III-V族材料系统, 然而由于III-V族材料存在核自旋引起的超精细相互作用, 严重限制了退相干时间的延长[7-9], 使其发展受限. 硅和锗等IV族材料因为可以通过纯化获得不含核自旋的硅28和锗72等同位素纯化材料, 可以避免由核自旋引起的超精细相互作用, 从而可以大幅增加量子比特的退相干时间而受到了研究者们的青睐[10-12]. 尤其是锗, 一方面它与硅兼容, 另一方面它具有高空穴迁移率[13]、低有效质量、强自旋-轨道相互作用[14]以及与金属能形成良好接触等优点. 甚至有理论预言在锗/硅纳米线中存在超强的自旋-轨道相互作用[15], 强自旋-轨道相互作用便于对量子比特进行快速电学操控, 并且通过和s波超导体的结合可望观测到马约拉纳费米子[16], 因此, 锗/硅纳米线是实现高性能自旋甚至拓扑量子比特的材料系统. 最近在一维锗量子材料中实现了空穴型量子比特[17], 还观测到近邻效应诱导的硬带隙超导电性[18].
然而锗纳米线的大规模可控制备依然是个难题. 制备纳米线的方法主要有自上而下的纳米加工技术制备法、气-液-固化学气相沉积法以及分子束外延生长方法等. 纳米加工技术可以获得亚10 nm的纳米线, 且纳米线排列整齐, 然而纳米加工过程的刻蚀会导致纳米线表面粗糙, 严重影响纳米线的质量[19]. 化学气相沉积法[20,21]可以高效获得大面积的纳米线, 但一般需要使用金属作为催化剂, 金属会不可避免地污染半导体纳米线, 而且纳米线是非面内生长, 因此如何转移和有序排列这些纳米线也是个很大的难题. 利用分子束外延生长方法, 选择合适的锗生长温度和沉积量, 通过原位降温退火, 可以在硅衬底上实现锗纳米线的无催化剂大规模面内生长[22], 有效地避免了金属污染和转移的难题, 同时又能够与传统硅工艺相兼容, 为量子比特器件的制备提供了全新的材料平台. 此后在这种锗纳米线材料中先后实现了单量子点、双量子点与超导微波谐振腔间的耦合[23,24], 成功实现了第一个锗空穴自旋量子比特[17]. 然而锗纳米线在硅衬底上的分布是随机的, 不利于量子器件的寻址和集成, 因此在硅衬底上获得面内定位生长的锗纳米线成为解决上述问题的关键. 通过在硅图形衬底上的定位生长是获得有序锗量子材料的有效方法, 例如可以通过刻蚀出洞来定位生长锗量子点[25,26]; 锗硅纳米线方面, 可在条状结构的硅(001)[27]或斜切硅(1 1 10)[28]图形衬底上沉积锗硅合金, 获得紧密排列的锗硅纳米线束, 然而这种方法无法获得分立的单根纳米线.
基于以上研究现状, 本文探究了利用分子束外延(MBE)生长技术, 通过低温沉积硅锗合金以及升温退火的方法, 成功的在硅图形衬底上获得了周期性有序排列的锗硅纳米线, 定性地解释了其生长过程和机理, 并进一步探讨了温度、锗硅合金比例以及图形周期等对锗硅纳米线的影响, 为获得更高质量且有序排列的锗纳米线提供了思路, 为进一步实现器件的集成提供了可能的材料平台.
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采用电子束曝光技术和反应离子刻蚀技术, 在硅(001)衬底上获得了周期性排列的凹槽. 图形衬底表面的原子力显微镜图(AFM)如图1(a)所示, 凹槽尺寸均匀, 其宽度为60 nm, 深度为6 nm, 长度为2 μm, 周期为1 μm, 凹槽沿[100]或[010]方向. 硅图形衬底经过RCA(Radio Corporation of America)清洗[29]之后, 首先用5%的氢氟酸浸泡1 min, 去掉表面的二氧化硅层, 同时在硅表面形成氢钝化层, 经过在进样腔预烘烤后传入IV族MBE生长腔, 然后升温至720 ℃保持8 min, 去除硅片表面的氢原子钝化层, 最后在330 ℃到400 ℃以1 Å/s的速率生长60 nm的硅缓冲层, 修复微纳加工引入的缺陷. 硅缓冲层的AFM图如图1(b)所示, 其深度变为约4 nm, 但是宽度却大幅度增加, 变为约160 nm. 此外, 从图1(b)的插图可以看出, 沉积硅缓冲层后, 凹槽末端由原来的无明显取向(如图1(a)插图所示)变为了沿
$ [1\;\bar1\;0] $ 与[1 0]两个垂直方向, 这是由于硅缓冲层的沉积导致凹槽末端晶面向硅的稳定晶面{11n}[30]演化, 从而使凹槽末端侧壁沿$ [1\;\bar1\;0] $ 与[1 0]方向, 这些结果与之前的研究结果一致[25].
图 1 生长硅缓冲层前(a)和生长硅缓冲层后(b)硅周期性凹槽结构的表面AFM图, 插图分别为生长硅缓冲层前后凹槽末端的放大图
Figure 1. AFM image of the trench-patterned Si substrate before (a) and after (b) the growth of Si buffer layer, insets are the zoom-in images of one end of a trench before and after the Si buffer layer, respectively.
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沉积完上述硅缓冲层后, 将衬底温度升至450 ℃, 继续沉积6 nm的Si67Ge33合金薄膜, 然后将衬底温度升至510 ℃, 原位退火1 h, 在图形衬底上获得了面内有序排列的锗硅纳米线, 其表面AFM图如图2(a)所示, 纳米线在面内排列整齐, 尺寸均匀, 图2(b)与图2(c)分别为单根纳米线的AFM图以及表面线扫描图, 由图可知, 纳米线位于凹槽底部, 其横截面为三角形, 高度约为7 nm, 侧壁倾角为11.3°, 因此纳米线具有两个稳定的(105)晶面.
图 2 (a)硅衬底上有序锗硅纳米线的AFM图; (b)单根锗硅纳米线的AFM图; (c)单根纳米线的表面线扫描图, 图中标尺均为500 nm
Figure 2. (a) AFM image of ordered GeSi wires on trench patterned substrate; (b) AFM image of zoom-in individual GeSi nanowire; (c) AFM linescan along the cross-section of a GeSi nanowire. Inset scale bar: 500 nm.
比较图2(b)与图1(b)中凹槽的形貌可以看出, 其末端晶向由原来的
$ [1\;\bar1\;0] $ 与[10]方向转变成了沿[100](或[010])方向, 同时凹槽在沿线以及垂直于线方向的侧壁变得非常整齐, 这是由于沉积硅锗层后, 其晶面向锗的稳定晶面{10n}[31]转化, 在长时间退火后, 最终形成了稳定的{10n}晶面, 因此沿[100]或[010]方向变得非常整齐. 此外, 图2(b)中纳米线的两端尺寸明显偏大, 其高度约为8 nm, 这是在生长以及退火过程中, 凹槽两端的捕获面积大于中间区域的捕获面积, 有更多的原子向端点位置扩散聚集, 从而使纳米线末端尺寸偏大. -
为了理解锗硅纳米线的生长机理, 又研究了退火温度、锗硅比例以及图形周期对纳米线的影响.
首先, 在凹槽结构的图形衬底上, 在450 ℃沉积4 nm的Si67G33合金薄膜, 然后分别在450, 500, 510, 520, 530, 550 ℃退火1 h, 得到的纳米线表面AFM图如图3(a)—(f)所示. 从图中可知, 沉积一定厚度的硅锗合金, 退火温度为450 ℃时, 凹槽内没有出现纳米结构; 退火温度的升高到500, 510, 520 ℃时, 纳米线结构只出现在凹槽底部; 而退火温度进一步升高到530 ℃甚至550 ℃时, 纳米线同时出现在凹槽底部与凹槽边缘, 且有形成紧密排列的纳米线束的趋势. 也就是说, 低温生长的硅锗合金薄膜只有升温到特定温度区间退火, 才能出现只在槽内形成单根纳米线结构而其他区域没有结构的现象.
图 3 在硅凹槽结构图形衬底上沉积4 nm的Si67G33薄膜, 然后在不同温度退火后得到的样品表面AFM图 (a) 450 ℃; (b) 500 ℃; (c) 510 ℃; (d) 520 ℃; (e) 530 ℃; (f) 550 ℃
Figure 3. AFM images of the trench-patterned samples with 4 nm Si67Ge33 film after 1 h annealing at different temperatures: (a) 450 ℃; (b) 500 ℃; (c) 510 ℃; (d) 520 ℃; (e) 530 ℃; (f) 550 ℃.
进一步研究了硅锗薄膜中锗的含量对锗硅纳米线的影响, 在450 ℃分别生长了6 nm的Si68Ge32,Si66Ge34以及Si63Ge37合金薄膜, 然后升温到510 ℃退火1 h, 其表面AFM图如图4(a), (b)以及(c)所示. 当锗含量较低时(图4(a)), 即使升温退火也不会出现连续的纳米线结构; 增加锗含量, 凹槽中间形成纳米线, 如图4(b)及图2(a)所示; 当锗含量进一步增加时(图4(c)), 凹槽底部纳米线出现了不连续的现象, 凹槽内纳米线的尺寸明显减小, 且在凹槽边缘出现了纳米线结构. 因此, 锗含量必须合适才会出现纳米线结构, 且纳米线的形成对锗的含量非常敏感, 也就是说其生长窗口非常小.
图 4 固定薄膜厚度时, 锗的含量比例对纳米线结构的影响 (a) Si68G32; (b) Si66G34; (c) Si63G37
Figure 4. The influence of Ge concentration on the formation of SiGe wires when the thickness of SiGe film is fixed: (a) Si68G32; (b) Si66G34; (c) Si63G37.
最后研究了图形周期对于纳米线结构的影响, 如图5(a)和图5(b)是周期为2 μm与500 nm的硅图形衬底上得到的纳米线的表面AFM图. 具体生长条件是在450 ℃沉积6 nm的Ge67Si33合金薄膜, 然后升温到510 ℃退火1 h. 结合图5与图2(a)可以看出, 不同周期下纳米线的尺寸基本一致, 非常均匀, 说明该生长条件下锗硅纳米线生长是一个热力学决定的过程, 存在稳定的横向尺寸. 总之, 可以精确地利用凹槽的位置定位纳米线的位置, 获得均匀的锗硅纳米线, 纳米线的长度依赖于凹槽的长度, 即纳米线的长度可以达到几微米甚至毫米、厘米量级, 实现了纳米线的位置可控生长.
图 5 不同周期图形衬底上锗硅纳米线的表面AFM图 (a)周期为2 µm; (b)周期为500 nm
Figure 5. AFM images of GeSi wires on trench-patterned Si (001) with different pattern periods: (a) period of 2 µm; (b) period of 500 nm.
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在本实验中, 首先在450 ℃沉积一定厚度的Si67Ge33合金薄膜, 如果在450 ℃原位退火, 由于硅锗原子的表面扩散长度不够, 不会形成纳米线; 而升温至500—520 ℃退火处理时, 锗、硅原子的表面扩散长度增大, 当凹槽侧壁倾斜角度较小, 正如本实验中的情况, 凹槽位置能够提供最大的应变弛豫[32-34], 因此锗硅原子会在凹槽中优先成核形成具有(105)晶面的锗硅纳米线; 当退火温度进一步升高时, 如图3(e)与3(f)所示, 如参考文献中关于锗纳米线束的讨论[35,36], 凹槽内部首先形成纳米线, 由于温度升高会使更多的硅锗表面原子被激活发生扩散, 这些硅锗原子会以该纳米线为中心形成紧挨着的一根根的纳米线, 它们像波浪传播一样形成纳米线束甚至可以铺满整个表面, 这主要源于应变状态下的锗硅(105)晶面具有很低的表面能, (105)晶面铺满的表面可以降低系统表面能, 同时纳米线束的形成相对于形成同等数目的独立纳米线可以减小边缘的数目, 从而减小边缘能. 而纳米线之间出现的凹槽是由于纳米线在两侧边缘处产生了较大的压应变引起的, 与锗硅岛会在边缘产生凹槽的机制相同.
然后, 我们研究了硅锗薄膜中锗的含量对锗硅纳米线的影响, 因为成核的能垒ΔG*与体系晶格失配的4次方成反比[37,38], 当锗含量较低时, 如图4(a)所示, 晶格失配较小, 形成岛或凹槽结构的能垒较大; 当锗含量增大时, 如图4(b)所示, 晶格失配变大, 形成岛或者凹槽结构的能垒变低, 因此在凹槽中形成了纳米线; 当锗的含量进一步增大时, 硅锗原子表面扩散势垒增高[39,40], 扩散系数变小, 从而无法形成长的纳米线, 同时锗含量的增大会导致锗硅纳米线的弹性能增加从而横向尺寸变小, 如图4(c)所示.
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结合自上而下的纳米加工和自下而上的自组装技术, 利用分子束外延生长方法, 在硅(001)图形衬底上通过低温沉积硅锗合金再升温退火的方法, 实现了硅图形化衬底上锗硅纳米线在凹槽中的有序生长, 详细研究了退火温度、锗含量以及图形周期对纳米线的影响, 为锗纳米线位置、结构的可控制备及锗量子器件的集成提供了可能.
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Controllable growth of nanowires is a prerequisite for addressability and scalability of nanowire quantum devices. By combining top-down nanofabrication and bottom-up self-assembly, site-controlled GeSi nanowires with two (105) facets can be grown on Si (001) substrate with pre-patterned trenches. Trenches along the [100] or [010] crystallographic direction with 60 nm in width and 6 nm in height are fabricated on Si substrate by electron beam lithography and reactive ion etching. Subsequently, a 60-nm-thick Si buffer layer is grown at 330–400 ℃ on the patterned substrate to improve the surface quality. The facets at the tip of the trenches transform into (11n) after depositing the Si buffer layer. Self-organized GeSi nanowires form inside the trenches by depositing the 6-nm-thick Si67Ge33 film at 450 ℃ followed by 1 h annealing at 510 ℃. The GeSi nanowires are (105)-faceted with an average height of approximately 7 nm. Furthermore, we systematically study the influence of annealing temperature, Ge concentration and pattern period on the formation of site-controllable GeSi nanowire on a patterned Si (001) substrate. The GeSi nanowires can be formed only inside the trenches within a specific annealing temperature ranging from 500 ℃ to 520 ℃. It is also discovered that GeSi nanowires are very sensitive to Ge concentration, as they cannot form at lower Ge concentration due to a large nucleation energy barrier. In contrast, high Ge concentration will lead to the discontinuity of nanowires caused by higher atomic diffusion barrier. The generated GeSi nanowires in the trenches exhibit similar dimensions at different pattern periods, which indicates that the growth process is thermodynamically determined. Overall, we realize the controllable growth of the GeSi nanowires, while the length of nanowires can reach the millimeter even centimeter scales, replying on the patterned trench length. The above results offer a controllable growth method of the Ge nanowires, which could potentially lead to the scalability of the Ge quantum devices on Si substrates.
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Keywords:
- molecular beam epitaxy /
- qubit /
- patterned substrate /
- GeSi nanowires
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图 1 生长硅缓冲层前(a)和生长硅缓冲层后(b)硅周期性凹槽结构的表面AFM图, 插图分别为生长硅缓冲层前后凹槽末端的放大图
Fig. 1. AFM image of the trench-patterned Si substrate before (a) and after (b) the growth of Si buffer layer, insets are the zoom-in images of one end of a trench before and after the Si buffer layer, respectively.
图 2 (a)硅衬底上有序锗硅纳米线的AFM图; (b)单根锗硅纳米线的AFM图; (c)单根纳米线的表面线扫描图, 图中标尺均为500 nm
Fig. 2. (a) AFM image of ordered GeSi wires on trench patterned substrate; (b) AFM image of zoom-in individual GeSi nanowire; (c) AFM linescan along the cross-section of a GeSi nanowire. Inset scale bar: 500 nm.
图 3 在硅凹槽结构图形衬底上沉积4 nm的Si67G33薄膜, 然后在不同温度退火后得到的样品表面AFM图 (a) 450 ℃; (b) 500 ℃; (c) 510 ℃; (d) 520 ℃; (e) 530 ℃; (f) 550 ℃
Fig. 3. AFM images of the trench-patterned samples with 4 nm Si67Ge33 film after 1 h annealing at different temperatures: (a) 450 ℃; (b) 500 ℃; (c) 510 ℃; (d) 520 ℃; (e) 530 ℃; (f) 550 ℃.
图 4 固定薄膜厚度时, 锗的含量比例对纳米线结构的影响 (a) Si68G32; (b) Si66G34; (c) Si63G37
Fig. 4. The influence of Ge concentration on the formation of SiGe wires when the thickness of SiGe film is fixed: (a) Si68G32; (b) Si66G34; (c) Si63G37.
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