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随着3D NAND闪存向更高层数堆叠, 后栅工艺下, 金属钨(W)栅字线(WL)层填充工艺面临的挑战进一步增大. 由于填充路径增长, 钨栅在沉积过程中易产生空洞, 造成含氟(F)副产物的聚集, 引起氟攻击问题. 具体表现为, 在后续高温制程的激发下, 含氟副产物向周围结构扩散, 侵蚀其周边氧化物层, 导致字线漏电, 影响器件的良率及可靠性. 本文首先分析了在3D NAND闪存中氟攻击的微观原理, 并提出了通过低压退火改善氟攻击问题的方法. 接下来对平面薄膜叠层与三维填充结构进行常压与低压下的退火实验, 并使用多种方法对残留氟元素的浓度与分布进行表征. 实验结果表明, 适当条件下的低压退火, 使得钨栅中的残余氟有效地被排出, 可以有效降低字线的漏电指数, 提高3D NAND闪存的质量.In this work, the influence of fluorine (F) erosion on tungsten (W) gate process is studied, and the measure to mitigate the word line (WL) leakage resulting from F erosion in 3D NAND flash memory is proposed. As the number of layers in 3D NAND increases, the tungsten (W) gate word line (WL) layer fill process becomes more challenging in the post-gate process. As the fill path length increases, the tungsten gates become more susceptible to voiding during deposition, resulting in the accumulation of fluorine (F) by-products, and causing fluorine attack issues. In particular, under the influence of subsequent high-temperature processes, the by-products containing fluorine can diffuse into the surrounding structure and corrode the surrounding oxide layer. This leads to WL leakage, thereby affecting device yield and reliability. This paper begins by analyzing the microscopic principles of fluorine erosion in 3D NAND. We also propose a low-pressure annealing method to address the issue of fluorine erosion. Then, we conduct the experiments on annealing planar thin film stacks and 3D filled structures under atmospheric condition and low-pressure condition. We use various methods to characterize the concentration and distribution of residual fluorine elements. The experimental results demonstrate that under appropriate conditions, the residual fluorine in the tungsten gate can be effectively released by low-pressure annealing, thus reducing the leakage index of the word line. Additionally, as the outer CH is closer to the fluorine discharge channel, the influence of low-pressure annealing on the outer CH is more pronounced than on the inner CH. The low-pressure annealing can significantly reduce the fluorine content in the tungsten gate. This method can also mitigate the issue of fluorine attack oxides and reducethe WL leakage. Using low-pressure annealing treatment can also enhance the quality of 3D NAND flash technology.
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图 1 氟攻击问题示意图, 说明 W 栅中剩余 F 对氧化层的腐蚀机理(O-N-O 分别代表氧化物隧穿层、氮化物俘获层和氧化物阻挡层)
Fig. 1. Schematic diagram of fluorine attacks oxide, illustrating the corrosion mechanism of the oxide layer in the W gate (O-N-O represents the oxide tunneling layer, nitride capture layer and oxide barrier layer, respectively).
图 2 (a) Y-Z 方向的3D NAND阵列结构示意图; (b) 3D NAND阵列的制造工艺流程(外排孔靠近阵列公共源区, 内排孔远离阵列公共源区)
Fig. 2. (a) Schematic diagram of the 3D NAND array structure in the Y-Z direction; (b) the manufacturing process of 3D NAND array (the outer hole is close to the array common source area, and the inner hole is far away from the array common source area).
图 3 (a) W 沉积后退火示意图, 说明了高温热处理可以将剩余 F 排出; (b)常压退火及低压退火后 W 层中的 F元素二次离子质谱分析图
Fig. 3. (a) Schematic diagram of annealing after W deposition, illustrating the thermal processing can discharge the remaining F element; (b) SIMS of the F element in the W layer after AP and LP
图 4 氧化物阻挡层中的 F 元素 EELS 映射图 (a)常压退火, 内排孔; (b)常压退火, 外排孔; (c)低压退火, 内排孔; (d)低压退火, 外排孔
Fig. 4. The EELS map of F element in the oxide barrier layer: (a) AP, inner hole; (b) LP, outer hole; (d) LP, inner hole; (b) AP, outer hole.
图 5 相同 WL 在常压和低压退火处理后的 WL 漏电指数
Fig. 5. The WL leakage index of the same WL at AP and LP annealing.
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[1] Compagnoni C M, Goda A, Spinelli A S, Feeley P, Lacaita A L, Visconti A 2017 Proc. IEEE 105 1609
Google Scholar
[2] Kim H, Ahn S J, Shin Y G, Lee K, Jung E 2017 IEEE International Memory Workshop (IMW) Monterey, California, May 14–17, 2017 p1
[3] Vasilyev V, Chung S H, Song Y W 2007 Solid State Technol. 50 53
[4] Xu Q, Luo J, Wang G, Yang T, Li J, Ye T, Chen D, Zhao C 2015 Microelectron. Eng. 137 43
Google Scholar
[5] Moon J, Lee T Y, Ahn H J, Lee T I, Hwang W S, Cho B J 2018 IEEE Trans. Electron Dev. 66 378
Google Scholar
[6] Bakke J, Lei Y, Xu Y, Daito K, Fu X, Jian G, Wu K, Hung R, Jakkaraju R, Breil N 2016 IEEE International Interconnect Technology Conference/Advanced Metallization Conference (IITC/AMC) San Jose, California, USA, May 23–26, 2016 p108
[7] Lee J H, Hidayat R, Ramesh R, Roh H, Nandi D K, Lee W J, Kim S H 2022 Appl. Surf. Sci. 578 152062
Google Scholar
[8] Kim C H, Rho I C, Kim S H, Han I K, Kang H S, Ryu S W, Kim H J 2009 J. Electrochem. Soc. 156 H685
Google Scholar
[9] Subramaniyan A, Luppi D F, Makela N, Bauer L, Madan A, Murphy R, Baumann F, Kohli K, Parks C 2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Saratoga Springs, New York, USA, May 16–19, 2016 p313
[10] Song Y J, Xia Z L, Hua W Y, Liu F, Huo Z L 2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Beijing, China, November 21–23, 2018 p120
[11] Mistry K, Allen C, Auth C, Beattie B, Bergstrom D, Bost M, Brazier M, Buehler M, Cappellani A, Chau R 2007 IEEE International Electron Devices Meeting Washington, DC, December 10–12, 2007 p247
[12] Leusink G, Oosterlaken T, Janssen G, Redelaar S 1993 Thin Solid Films 228 125
Google Scholar
[13] Kodas T T, Hampden S M J 2008 The Chemistry of Metal CVD (John Wiley & Sons) p112
[14] Klaus J, Ferro S, George S 2000 Thin Solid Films 360 145
Google Scholar
[15] Hidayat R, Chowdhury T, Kim Y, Kim S, Mayangsari T R, Kim S H, Lee W J 2021 Appl. Surf. Sci. 538 148156
Google Scholar
[16] Park H, Lee S, Kim H J, Woo D, Lee J M, Yoon E, Lee G D 2018 RSC Adv. 8 39039
Google Scholar
[17] Schulze S, Wolansky D, Katzer J, Schubert M, Costina I, Mai A 2018 IEEE Trans. Semicond. Manuf. 31 528
Google Scholar
[18] Kalanyan B, Lemaire P C, Atanasov S E, Ritz M J, Parsons G N 2016 Chem. Mater. 28 117
Google Scholar
[19] Lee J H, Kim H W, Park I H, Cho S, Lee G S, Kim D H, Yun J G, Kim Y, Lee J D, Park B G 2006 IEEE Nanotechnology Materials and Devices Conference New York, USA, October 22–25, 2006 p638
[20] Yang Y, Zhu H, Meng X, Jin L, Wang C, Wang S, Feng S, Guo C, Zhang Y 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) Qingdao, China, October 31–November 3, 2018 p1
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