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中国物理学会期刊

基于改进遗传算法设计的超紧凑型片上硅光隔离器

CSTR: 32037.14.aps.74.20241228

Ultra-compact on-chip silicon photonics isolator designed using modified genetic algorithm

CSTR: 32037.14.aps.74.20241228
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  • 片上集成型光隔离器的定向光传输特性在光通信、光信号处理等领域有广泛的应用价值. 本文通过改进遗传算法, 引入分段的适应度函数(阶段1设定隔离度; 阶段2设定插入损耗), 并建立基因库; 在仅为4.2\text μm\times 3\text μm的区域内获得了一种超紧凑的光隔离器方案. 在标准的绝缘体上硅(silicon on insulator, SOI)基片上, 通过设置5种直径(60 nm, 120 nm, 180 nm, 240 nm, 300 nm)的刻蚀圆孔排布, 在1550 nm TE偏振模式下, 取得了隔离度约为31 dB、插入损耗约为2 dB的结果; 在1550 nm TM偏振模式下, 取得了隔离度约为38 dB、插入损耗为2 dB的结果. 还进一步分析了不同尺寸组对隔离器性能的影响. 这些结果对于发展超小尺寸、高集成度的片上光信号定向传输方案有促进作用.

     

    The directional optical transmission characteristics of on-chip integrated optical isolators have wide applications in fields such as optical communication and optical signal processing. At early stage, various schemes of on-chip optical isolators have been developed, such as single-crystal magneto-optical pomegranate scheme, and silicon nitride (Si3N4) micro-ring resonators. However, there is still lack of compact on-chip optical isolator solutions. Here, a compact and integrated silicon optical isolator on a standard silicon on insulator (SOI) substrate is proposed and designed by intelligent algorithms and a variety of micro-nano circular vias. A modified genetic algorithm is developed, a segmented design fitness function is induced, and a gene library is established to obtain an ultra-compact optical isolator scheme with a size of only 4.2 μm×3 μm. On a standard silicon on insulator substrate, a linear passive isolation scheme is achieved by etching circular holes with five different diameters: 60 nm, 120 nm, 180 nm, 240 nm, and 300 nm. In the TE polarization mode, the design achieves an isolation degree of approximately 31 dB and an insertion loss of about 2 dB. Furthermore, in TM polarization mode, the design achieves an isolation degree of approximately 38 dB and an insertion loss of 2 dB; Finally, the influence of different size groups on the performance of isolators is analyzed. The results show that the smaller the circular hole structure, the better the isolation performance is. However, at the same time, we also need to consider the real silicon etching process requirements. In practice, holes that are too small are difficult to etch the effects of etching penetration at 10 nm, 20 nm and 30 nm between circular vias on the performance of the isolator are also evaluated, and the preliminary results show that the etching penetration caused by the more mature 30 nm etching process is acceptable. Therefore, considering all factors, it is recommended that the minimum circular hole size be 30 nm and the minimum distance adjacent circular holes be 30 nm. These results can promote the development of highly integrated and ultra-small on-chip optical signal directional transmission schemes.

     

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