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Based on the distributed interconnect power model, a novel dynamic power model is presented in this paper, in which a non-uniform interconnection structure is adopted. This model takes into account the self-heating effect and is constrained by delay, bandwidth, area, minimum interconnect width and minimum interconnect space. The validity of the proposed model is verified by 90 nm and 65 nm complementary metal-oxide semiconductor technology. The results indicate that the proposed model can cause a power consumption reduction as high as 35%, and yet the delay, area, and bandwidth are not deteriorated, when compared with the conventional power model. The proposed optimal model can be used for designing large scale interconnect router and clock network in network-on-chip structure.
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Keywords:
- distributed interconnect /
- optimal power model /
- self-heating effect /
- non-uniform interconnection
[1] Semiconductor Industry Association 2010 International Technology Roadmap for Semiconductors 2010 (ITRS 2010)
[2] Uchino T, Cong J 2002 IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 21 763
[3] Zhu Z M, Zhong B, Yang Y T 2010 Acta Phys. Sin. 59 4895 (in Chinese) [朱樟明, 钟波, 杨银堂 2010 物理学报 59 4895]
[4] Sahoo S, Data M, Kar R 2011 Proceedings of the Second International Conference on Emerging Applications of Information Technology Kolkata, India, February 19-20, 2011 p379
[5] Zhou Q M, Elmore K M 2006 ACM/IEEE Design Automation Conf. San-Francisco, CA, USA, July 24-28, 2006 p965
[6] Zhu Z M, Zhong B, He B T, Yan Y T 2009 Acta Phys. Sin. 58 7124 (in Chinese) [朱樟明, 钟波, 赫报田, 杨银堂 2009 物理学报 58 7124]
[7] Chen P C, Chen P Y, Wong D F 1996 Proceedings of 33rd Design Automation Conference Las Vegas, NV, USA, June 3-7, 1996 p487
[8] Ni M, Memik S O M 2007 Proc. Des. Autom. Test Eur. DATE Nice Acropolis, France, April 16-20, 2007 p1373
[9] Ajami A H, Banerjee K, Pedram M 2005 IEEE Trans. Comput. -Aided Des. Integr. Circuits Syst. 24 849
[10] Lee Y M, Chen C C P, Wong D F 2002 IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 49 1671
[11] El-moursy M A, Fridman E G 2005 IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 13 971
[12] Kar R, Maheshwari V, Agarwal V, Mal A K, Bhattacharjee A 2010 IEEE Symposium on Industrial Electronics and Applications Penang, Malaysia, October 3-5, 2010 p436
[13] El-moursy M A, Fridman E G 2007 Integr. VLSI J. 40 461
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[1] Semiconductor Industry Association 2010 International Technology Roadmap for Semiconductors 2010 (ITRS 2010)
[2] Uchino T, Cong J 2002 IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 21 763
[3] Zhu Z M, Zhong B, Yang Y T 2010 Acta Phys. Sin. 59 4895 (in Chinese) [朱樟明, 钟波, 杨银堂 2010 物理学报 59 4895]
[4] Sahoo S, Data M, Kar R 2011 Proceedings of the Second International Conference on Emerging Applications of Information Technology Kolkata, India, February 19-20, 2011 p379
[5] Zhou Q M, Elmore K M 2006 ACM/IEEE Design Automation Conf. San-Francisco, CA, USA, July 24-28, 2006 p965
[6] Zhu Z M, Zhong B, He B T, Yan Y T 2009 Acta Phys. Sin. 58 7124 (in Chinese) [朱樟明, 钟波, 赫报田, 杨银堂 2009 物理学报 58 7124]
[7] Chen P C, Chen P Y, Wong D F 1996 Proceedings of 33rd Design Automation Conference Las Vegas, NV, USA, June 3-7, 1996 p487
[8] Ni M, Memik S O M 2007 Proc. Des. Autom. Test Eur. DATE Nice Acropolis, France, April 16-20, 2007 p1373
[9] Ajami A H, Banerjee K, Pedram M 2005 IEEE Trans. Comput. -Aided Des. Integr. Circuits Syst. 24 849
[10] Lee Y M, Chen C C P, Wong D F 2002 IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 49 1671
[11] El-moursy M A, Fridman E G 2005 IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 13 971
[12] Kar R, Maheshwari V, Agarwal V, Mal A K, Bhattacharjee A 2010 IEEE Symposium on Industrial Electronics and Applications Penang, Malaysia, October 3-5, 2010 p436
[13] El-moursy M A, Fridman E G 2007 Integr. VLSI J. 40 461
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