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原子芯片的基本原理、关键技术及研究进展

李沫 陈飞良 罗小嘉 杨丽君 张健

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原子芯片的基本原理、关键技术及研究进展

李沫, 陈飞良, 罗小嘉, 杨丽君, 张健

Fundamental principles, key enabling technologies, and research progress of atom chips

Li Mo, Chen Fei-Liang, Luo Xiao-Jia, Yang Li-Jun, Zhang Jian
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  • 飞速发展的激光冷却、囚禁与操控中性原子的理论和实验技术不仅促进了人们对微观物质运动规律的认知, 而且在精密测量和量子信息领域催生了多项颠覆性的器件与应用. 不同于传统复杂庞大的原子光学实验装置, 原子芯片通过在硅等基底上制备的表面微纳结构或器件来精准控制磁场、电场或光场, 从而在小尺度、低功耗条件下实现对原子的强束缚与相干操控, 被认为是一种稳定、精确、功能及扩展性强大的原子及其量子态片上实验平台, 具有广泛且重大的应用价值. 本文首先简要回顾了原子芯片的发展历程, 然后介绍了基于载流导线的微势阱及微导引实现原子芯片的基本原理, 并着重讨论了基于载流导线的原子芯片制备技术、测试方法和集成的全链条关键实现技术. 随后, 本文综述了各国与原子芯片相关的研究计划布局和主要应用进展, 指出原子芯片走向实用面临的挑战性问题, 并对其未来发展进行了展望.
    The laser cooling, trapping and manipulating of neutral atoms has become a valuable tool for scientists, providing innovative ways to probe the nature of reality and giving rise to transformative devices in the fields of precise measurement and quantum information processing. Unlike traditional complex and bulky atomic experimental facilities, atom chips, through the design, fabrication of surface-patterned microstructures, and the integration of devices on the substrates, can precisely control the magnetic, electric or optical fields on a micro-nano scale with low power consumption. It can realize strong trapping as well as coherent atomic manipulation. Since atom chip was first proposed twenty years ago, it has built a robust quantum platform for miniaturizing and integrating quantum optics and atomic physics tools on a chip. In this paper, first, we briefly review the development history of atom chips, then introduce the basic knowledge of micro potential traps and micro guides based on on-chip current-carrying wires. Afterwards, the key technologies about the chip material, design, fabrication, characterization and integration of atom chips are discussed in detail. We not only focus on the currently most active and successful areas - current carrying wires, but also look at more visionary approaches such as to the manipulation of atoms with real nano structures, say, carbon nano tubes. The design and fabrication principles of ideal atom chips are discussed as well. In the forth part, the worldwide plans and research projects involving with atom chip technologies are summarized, showing that many countries see this as an important foundational technology. Following that, the major developments in the application fields including atom clocks, atom interferometer gyroscope, cold atom gravimeter, etc are described. Finally, the challenges faced by atom chips towards practical application are pointed out and the prospects for their subsequent development are depicted.
      通信作者: 李沫, limo@uestc.edu.cn
    • 基金项目: 国家自然科学基金(批准号: 61875178)、国家自然科学基金委员会-中国工程物理研究院(NSAF)联合基金(批准号: U1730126)和科学挑战专题(批准号: TZ2018003-3)资助的课题
      Corresponding author: Li Mo, limo@uestc.edu.cn
    • Funds: Project supported by the National Natural Science Foundation of China (Grant No. 61875178), the National Natural Science Foundation of China and China Academy of Engineering Physics Joint Fund (NSAF) (Grant No. U1730126), and the Science Challenge Project (Grant No. TZ2018003-3)
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  • 图 1  (a)由U形阱形成的四极磁阱; (b)由Z形阱形成的IP阱[3]

    Fig. 1.  (a) Quadrupole trap by U configuration; (b) Ioffe-Pritchard trap by Z configuration[3].

    图 2  (a) Dimple阱; (b) H形阱[20]

    Fig. 2.  (a) Dimple trap; (b) H-type trap[20].

    图 3  四种平面Ioffe阱的方案[22]

    Fig. 3.  Four planar Ioffe trap configurations[22].

    图 4  多种原子传送带结构[23-25]

    Fig. 4.  Multiple configurations of atom conveyor belts[23-25].

    图 5  基于(a)金字塔结构[29], (b)光栅结构[33]的芯片微MOT

    Fig. 5.  Micro-MOTs chip based on (a) micro-paramide arrays[29] and (b) gratings[33].

    图 6  (a) 侧边导引; (b) 共面成对同向载流的侧边导引; (c) 共面成对异向载流的侧边导引; (d)三线导引. 图中S为导线间距

    Fig. 6.  (a) Side guide; (b) two-wire side with co-propagating currents; (c) two-wire side guide with opposing current directions; (d) three-wire guide. S is the distance between wires.

    图 7  弗吉尼亚大学设计的MOT[41]

    Fig. 7.  Magnetic trap assembly proposed by University of Virginia[41].

    图 8  原子芯片上的Y形分束和X形分束[22]

    Fig. 8.  Beam splitter for guided atoms using Y-shaped and X-shaped current carrying wires[22].

    图 9  原子芯片上基于射频场的双势阱物质波分束[52]

    Fig. 9.  Matter-wave beam splitter by dressing RF-fields on chip[52].

    图 10  (a) 双层CNT原子芯片示意图; (b) 原子力显微镜(AFM)下CNT及其与Z形导线的接触[61]

    Fig. 10.  (a) Schematic representation of the two layer CNT atom chip; (b) atomic force microscope image of a CNT fabricated and contacted for use as a Z-shaped wire trap[61].

    图 11  原子芯片上载流导线的制备方法 (a) 剥离法; (b) 刻蚀法

    Fig. 11.  Fabrication methods of the on-chip current-carrying wires: (a) Stripping method; (b) etching method.

    图 12  基于不同封装工艺的原子芯片 (a) 针对传统真空法兰电极接口的芯片封装形式; (b) 超高真空胶; (c) 阳极键合[67]; (d) 软钎焊

    Fig. 12.  Atom chips based on different packaging processes: (a)Traditional vacuum package; (b) ultra-high vacuum adhesive; (c) anode adhesive[67]; (d) soft soldering.

    图 13  基于冷原子干涉的原子芯片陀螺仪基本流程

    Fig. 13.  Basic process of gyroscope based on cold atom interference on chip.

    图 14  Honeywell提出的水平方向集成的芯片级原子钟方案 (a) 原子物理集成部分; (b) 蒸汽室与光路的集成[76]

    Fig. 14.  Horizontally integrated design for a chip-scale atomic clock physics package: (a) Schematic of physics package and (b) photograph of vapor cell integrated into optical path[76].

    图 15  高度集成化的原子芯片量子陀螺仪构想[77]

    Fig. 15.  Futuristic visions of highly integrated atom chips for quantum gyroscope[77].

    图 16  C-SCAN的概念图[78]

    Fig. 16.  Schematic scheme of C-SCAN[78].

    图 17  美国DARPA的A-PHI计划框架

    Fig. 17.  Framework of A-PHI of DARPA.

    图 18  哈佛大学提出的直线形宏观磁导引等效“8”字形的闭合回路冷原子干涉陀螺仪[83]

    Fig. 18.  Schematic of a moving-guide with a ‘folded figure 8’ configuration for creating an atom gyroscope with multiple-turn interfering paths by Harvard University[83].

    图 19  美国弗吉尼亚大学基于芯片上闭合环形原子波导实现BEC干涉与转动测量[89]

    Fig. 19.  The rotational information experimental results of BEC atomic interferometry based on Sagnac effects by University of Virginia[89].

    图 20  基于原子芯片的喷泉式重力仪[91]

    Fig. 20.  Atom-chip fountain gravimeter[91].

    图 21  用于量子模拟的FePt永磁体纳米磁晶格原子芯片[96]

    Fig. 21.  The magnetic potential in arbitrary units above an magnetized patterned layer of FePt[96].

    图 22  联邦物理技术研究院和汉诺威大学合作报道的离子阱芯片[97]

    Fig. 22.  Multilayer ion trap chip by Germany[97].

    图 23  JPL和NASA发射到空间站的原子芯片[103,104]

    Fig. 23.  Atom chip launch to the space station by JPL and NASA[103,104].

    表 1  基于原子芯片的部分应用

    Table 1.  Applications based on atom chips.

    应用类型应用领域
    基础物理研究国家安全国民经济
    原子陀螺仪航空、航天、航海、
    潜艇、导弹导航
    自动驾驶, 手机定位导航
    原子加速度计广义相对论等效原理验证、行星科学航空、航天、航海、
    潜艇、导弹导航
    自动驾驶, 手机导航
    原子干涉重力仪万有引力常数测试导航煤、石油、天然气等资源勘探、
    地下遗迹探测、手机手势识别
    量子计算和量子模拟基础量子物理问题研究密码破译, 信息安全高性能计算
    芯片级原子钟广义相对论等效原理验证、引力波探测、
    暗物质探测、精细结构常数变化测试
    授时, 航空航天地貌测绘等
    芯片级原子磁力计潜艇探测矿石探测、人体健康检测
    下载: 导出CSV
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  • 收稿日期:  2020-09-21
  • 修回日期:  2020-11-04
  • 上网日期:  2021-01-15
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