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基于对偶单元法的三维集成微系统电热耦合分析

曹明鹏 吴晓鹏 管宏山 单光宝 周斌 杨力宏 杨银堂

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基于对偶单元法的三维集成微系统电热耦合分析

曹明鹏, 吴晓鹏, 管宏山, 单光宝, 周斌, 杨力宏, 杨银堂

Electrothermal coupling analysis of three-dimensional integrated microsystem based on dual cell method

Cao Ming-Peng, Wu Xiao-Peng, Guan Hong-Shan, Shan Guang-Bao, Zhou Bin, Yang Li-Hong, Yang Yin-Tang
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  • 随着三维集成微系统集成度和功率密度的提高, 同时考察电设计与热管理的多场耦合分析势在必行. 本文面向三维集成微处理器系统, 通过改进的对偶单元法(dual cell method, DCM)实现了系统的快速电热分析. 该方法通过引入泄漏功率、材料系数随温度的耦合, 相比于传统有限元法在更新以及组装本构矩阵上有更大的优势. 仿真验证表明, 本文所采用的算法相比传统有限元法仿真速度提升了约30%. 在考虑了材料系数以及泄露功率热耦合因素后, 系统热点温度相对于考虑耦合前上升了20.8 K. 最后采用本文所提出算法对三维集成微处理器系统进行布局研究, 比较了硅通孔阵列常规布局和集中布局在处理器核心下方两种布局方式对上下层芯片热点温度的影响, 研究了功率不均匀分配对两种布局的影响.
    With the improvement of the integration and power density of three-dimensional integrated microsystem, it is imperative to simultaneously investigate the multi-field coupling analysis of electrical design and thermal management. This paper is to investigate a three-dimensional integrated microprocessor system and realize the rapid electrothermal analysis of the system through an improved dual cell method (DCM). This method decomposes the constitutive matrix into a constant matrix and a temperature-dependent matrix by introducing the coupling of leakage power and material coefficients with temperature. In the calculation, only the temperature-dependent matrix needs to be updated and assembled, which makes the calculation speed faster than the traditional finite element method. The simulation results show that the speed of the proposed algorithm is improved by about 30% compared with that of the traditional finite element method. After considering the thermal coupling factors of material coefficient and leakage power, the hot spot temperature of the system increases by 20.8 K compared with before coupling. Finally, the algorithm proposed in this paper is used to study the layout of three-dimensional integrated microprocessor system. The influence of TSV array conventional layout and centralized layout under the processor core(core-layout) on the hot spot temperature of upper and lower chips are compared, and the influences of uneven power distribution on the two layouts are studied. The results show that compared with the conventional layout of TSV array, the core-layout can reduce the hot spot temperature of processor, but it will aggravate the hot spot problem of DRAM at the same time. And when the power is not evenly distributed on the four cores, the hot spot of DRAM under the core-layout will be more seriously affected. In conclusion, the algorithm model proposed in this paper can quickly analyze the electrothermal coupling problem of 3D integrated microsystem, realize the hot spot prediction of the system, and provide theoretical guidance for designing the chip layout of 3D integrated microsystem.
      通信作者: 吴晓鹏, xpwu@mail.xidian.edu.cn
    • 基金项目: 国防基础科学研究计划(国防科工局稳定支持基金) (批准号: 614280620200201)、国家自然科学基金(批准号: 62074121, 62034002)、陕西省自然科学基金(批准号: 2019GY-010)、陕西省教育厅科研计划(批准号: 20JY018)和中央高校基本科研业务费专项资金(批准号: XJS191101, XJS191106)资助的课题
      Corresponding author: Wu Xiao-Peng, xpwu@mail.xidian.edu.cn
    • Funds: Project supported by the National Defense Basic Scientific Research Program of China (the Stability Support Fund of the State Administration of Science, Technology and Industry for National Defense) (Grant No. 614280620200201), the National Natural Science Foundation of China (Grant Nos. 62074121, 62034002), the Natural Science Foundation of Shaanxi Province, China(Grant No. 2019GY-010), Scientific Research Program Funded by Shaanxi Provincial Education Department, China (Grant No. 20JY018), and the Fundamental Research Funds for the Central Universities (Grant Nos. XJS191101, XJS191106)
    [1]

    Benkart P, Kaiser A, Munding A, Bschorr M, Pfleiderer H J, Kohn E, Heittmann A, Huebner H, Ramacher U 2005 IEEE Des. Test Comput. 22 512Google Scholar

    [2]

    P op, E 2010 Nano Res. 3 147Google Scholar

    [3]

    Li S, Ahn J H, Strong R D, Brockman J B, Tullsen D M, Jouppi N P 2010 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) New York, United states, December 12–16, 2009 p469

    [4]

    Wang X P, Yin W Y, He S 2010 IEEE Trans. Electron Devices 57 1382Google Scholar

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    冯永平, 崔俊芝, 邓明香 2009 物理学报 58 327Google Scholar

    Feng Y P, Cui J Z, Deng M X 2009 Acta Phys. Sin. 58 327Google Scholar

    [6]

    Xie J Y, Swaminathan M 2014 IEEE Trans. Compon. Pack. Manuf. Technol. 4 588Google Scholar

    [7]

    Lu T J, Jin J M 2014 IEEE Trans. Compon. Pack. Manuf. Technol. 4 1684Google Scholar

    [8]

    Sai M P D, Yu H, Shang Y, Tan C S 2013 IEEE Trans. Comput-Aided Des. Integr. Circuits Syst. 32 1734Google Scholar

    [9]

    王存海, 郑树, 张欣欣 2020 物理学报 69 034401Google Scholar

    Wang C H, Zheng S, Zhang X X 2020 Acta Phys. Sin. 69 034401Google Scholar

    [10]

    Wang D W, Zhao W S, Chen W C, Zhu G D, Xie H, Gao P Q, Yin W Y 2019 IEEE Trans. Electron Devices 66 5117Google Scholar

    [11]

    柴泾睿 2019 博士学位论文 (西安: 西安电子科技大学)

    Chai J R 2019 Ph. D. Dissertation (Xi'an: Xidian University) (in Chinese)

    [12]

    Lin S G, Chrysler R, Mahajan V K.De K, Banerjee K 2007 IEEE Trans. Electron Devices 54 3342Google Scholar

    [13]

    Lin S G, Chrysler R, Mahajan V K.De K, Banerjee K 2007 IEEE Trans. Electron Devices 54 3351Google Scholar

    [14]

    Pi Y D, Wang N Y, Chen J, Miao M, Jin Y F, Wang W 2018 Int. J. Heat Mass Transfer 120 361Google Scholar

    [15]

    Chai J R, Dong G, Yang Y T 2019 IEEE Trans. Electron Devices 66 1032Google Scholar

    [16]

    Wang H, Wan J C, Tan S, Zhang C, Tang H, Yuan Y, Huang K H, Zhang Z H 2018 IEEE Trans. Comput. 67 617Google Scholar

    [17]

    Alotto P, Freschi F, Repetto M, Rosso C 2013 The Cell Method for Electrical Engineering and Multiphysics Problems (Berlin-Heidelberg: Springer-Verlag) pp11−113

    [18]

    Tonti E 2001 CMES-Comput. Model. Eng. Sci. 2 237Google Scholar

    [19]

    Freschi F, Giaccone L, Repetto M 2008 Compel-Int. J. Comput. Math. Electr. Electron. Eng. 27 1343Google Scholar

    [20]

    Alotto P, Freschi F, Repetto M 2010 IEEE Trans. Magn. 46 2959Google Scholar

    [21]

    Zhang Y, Sarvey T E, Bakir M S 2014 2014 International 3D Systems Integration Conference (3DIC) Kinsdale, Ireland, December 1–3, 2014 p14

    [22]

    Ma H, Yu D Q, Wang J 2014 Microelectron. Reliab. 54 425Google Scholar

    [23]

    Tavakkoli F, Ebrahimi S, Wang S, Vafai K 2016 Int. J. Heat Mass Transfer 97 337Google Scholar

    [24]

    Ren Z, Alqahtani A, Bagherzadeh N, Lee J 2020 IEEE Trans. Compon. Pack. Manuf. Technol. 4 599Google Scholar

  • 图 1  DCM求解传热问题流程图

    Fig. 1.  Flow chart of DCM solving heat transfer problem.

    图 2  对偶单元构建过程

    Fig. 2.  The process of dual unit construction.

    图 3  迭代算法流程图

    Fig. 3.  Flow chart of Iteration scheme.

    图 4  三维集成微处理器系统结构示意图

    Fig. 4.  Schematic diagram of the three-dimensional integrated microprocessor system.

    图 5  工作区域分布图 (a) DRAM芯片; (b) Intel i7处理器芯片

    Fig. 5.  Work area distribution map: (a) DRAM; (b) processor.

    图 6  不考虑耦合与考虑耦合时芯片温度分布 (a) DRAM; (b) 处理器

    Fig. 6.  Chip temperature distribution without considering coupling and considering coupling: (a) DRAM; (b)processor.

    图 7  两种不同的TSV阵列布局 (a) 常规布局; (b) Core-布局

    Fig. 7.  Two different TSV array layouts: (a) Conventional layout; (b) core layout.

    图 8  两种不同TSV阵列布局时处理器的温度分布

    Fig. 8.  Temperature distributions of processors with two different TSV arrays.

    图 9  Core-布局时DRAM温度分布图

    Fig. 9.  DRAM temperature distributions in core-layout.

    图 10  典型Core功率分配情况

    Fig. 10.  Typical core power allocation.

    图 11  不同功率分配下处理器芯片最高温度

    Fig. 11.  Maximum temperature of processor chip under different power allocation.

    图 12  不同功率分配下DRAM芯片最高温度

    Fig. 12.  Maximum temperature of DRAM chip under different power allocation.

    表 1  FEM与改进DCM的仿真时间对比

    Table 1.  Simulation time comparison between FEM and improved DCM.

    耦合情况仿真方法仿真时间仿真自由度
    不考虑耦合FEM60 S416941
    改进DCM55.3 S
    电热耦合FEM154 S
    改进DCM104.7 S
    下载: 导出CSV

    表 2  不同功率分配时仿真时间

    Table 2.  Improving simulation time of DCM and FEM with different power allocation.

    布局方式改进的DCM法仿真时间/sFEM平均时间/s自由度
    Case1Case2Case3Case4Case5Case6
    常规布局105.6106.1106.0105.7107.2104.8152.2416941
    Core布局100.9105.6102.6101.4101.9100.3144.9404345
    下载: 导出CSV

    表 3  不同功率分配下Core-布局相比于常规布局的芯片温度变化

    Table 3.  Chip temperature change of core layout compared with conventional layout under different power allocation.

    温度变化均匀Case1Case2Case3Case4Case5Case6
    处理器降温/K2.202.822.252.252.823.132.90
    DRAM升温/K4.296.695.776.126.097.837.88
    下载: 导出CSV
  • [1]

    Benkart P, Kaiser A, Munding A, Bschorr M, Pfleiderer H J, Kohn E, Heittmann A, Huebner H, Ramacher U 2005 IEEE Des. Test Comput. 22 512Google Scholar

    [2]

    P op, E 2010 Nano Res. 3 147Google Scholar

    [3]

    Li S, Ahn J H, Strong R D, Brockman J B, Tullsen D M, Jouppi N P 2010 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) New York, United states, December 12–16, 2009 p469

    [4]

    Wang X P, Yin W Y, He S 2010 IEEE Trans. Electron Devices 57 1382Google Scholar

    [5]

    冯永平, 崔俊芝, 邓明香 2009 物理学报 58 327Google Scholar

    Feng Y P, Cui J Z, Deng M X 2009 Acta Phys. Sin. 58 327Google Scholar

    [6]

    Xie J Y, Swaminathan M 2014 IEEE Trans. Compon. Pack. Manuf. Technol. 4 588Google Scholar

    [7]

    Lu T J, Jin J M 2014 IEEE Trans. Compon. Pack. Manuf. Technol. 4 1684Google Scholar

    [8]

    Sai M P D, Yu H, Shang Y, Tan C S 2013 IEEE Trans. Comput-Aided Des. Integr. Circuits Syst. 32 1734Google Scholar

    [9]

    王存海, 郑树, 张欣欣 2020 物理学报 69 034401Google Scholar

    Wang C H, Zheng S, Zhang X X 2020 Acta Phys. Sin. 69 034401Google Scholar

    [10]

    Wang D W, Zhao W S, Chen W C, Zhu G D, Xie H, Gao P Q, Yin W Y 2019 IEEE Trans. Electron Devices 66 5117Google Scholar

    [11]

    柴泾睿 2019 博士学位论文 (西安: 西安电子科技大学)

    Chai J R 2019 Ph. D. Dissertation (Xi'an: Xidian University) (in Chinese)

    [12]

    Lin S G, Chrysler R, Mahajan V K.De K, Banerjee K 2007 IEEE Trans. Electron Devices 54 3342Google Scholar

    [13]

    Lin S G, Chrysler R, Mahajan V K.De K, Banerjee K 2007 IEEE Trans. Electron Devices 54 3351Google Scholar

    [14]

    Pi Y D, Wang N Y, Chen J, Miao M, Jin Y F, Wang W 2018 Int. J. Heat Mass Transfer 120 361Google Scholar

    [15]

    Chai J R, Dong G, Yang Y T 2019 IEEE Trans. Electron Devices 66 1032Google Scholar

    [16]

    Wang H, Wan J C, Tan S, Zhang C, Tang H, Yuan Y, Huang K H, Zhang Z H 2018 IEEE Trans. Comput. 67 617Google Scholar

    [17]

    Alotto P, Freschi F, Repetto M, Rosso C 2013 The Cell Method for Electrical Engineering and Multiphysics Problems (Berlin-Heidelberg: Springer-Verlag) pp11−113

    [18]

    Tonti E 2001 CMES-Comput. Model. Eng. Sci. 2 237Google Scholar

    [19]

    Freschi F, Giaccone L, Repetto M 2008 Compel-Int. J. Comput. Math. Electr. Electron. Eng. 27 1343Google Scholar

    [20]

    Alotto P, Freschi F, Repetto M 2010 IEEE Trans. Magn. 46 2959Google Scholar

    [21]

    Zhang Y, Sarvey T E, Bakir M S 2014 2014 International 3D Systems Integration Conference (3DIC) Kinsdale, Ireland, December 1–3, 2014 p14

    [22]

    Ma H, Yu D Q, Wang J 2014 Microelectron. Reliab. 54 425Google Scholar

    [23]

    Tavakkoli F, Ebrahimi S, Wang S, Vafai K 2016 Int. J. Heat Mass Transfer 97 337Google Scholar

    [24]

    Ren Z, Alqahtani A, Bagherzadeh N, Lee J 2020 IEEE Trans. Compon. Pack. Manuf. Technol. 4 599Google Scholar

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出版历程
  • 收稿日期:  2020-09-30
  • 修回日期:  2020-11-06
  • 上网日期:  2021-03-26
  • 刊出日期:  2021-04-05

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